DocID024597 Rev 3 1383/1685
RM0351 Single Wire Protocol Master Interface (SWPMI)
1392
40.6.2 SWPMI Bitrate register (SWPMI_BRR)
Address offset: 0x04
Reset value: 0x0000 0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109876543210
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. BR[5:0]
rw rw rw rw rw rw
Bits 31:6 Reserved, must be kept at reset value
Bits 5:0 BR[5:0]: Bitrate prescaler
This field must be programmed to set SWP bus bitrate, taking into account the F
SWPCLK
programmed in the RCC (Reset and Clock Control), according to the following formula:
F
SWP
= F
SWPCLK
/ ((BR[5:0]+1)x4)
Note: The programmed bitrate must stay within the following range: from 100 kbit/s up to
2Mbit/s.
BR[5:0] cannot be written while SWPACT bit is set in the SWPMI_CR register.
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