DocID024597 Rev 3 331/1693
RM0351 Extended interrupts and events controller (EXTI)
336
Note: The configurable wakeup lines are edge-triggered. No glitch must be generated on these
lines. If a falling edge on a configurable interrupt line occurs during a write operation to the
EXTI_FTSR register, the pending bit is not set.
Rising and falling edge triggers can be set for the same interrupt line. In this case, both
generate a trigger condition.
12.5.5 Software interrupt event register 1 (EXTI_SWIER1)
Address offset: 0x10
Reset value: 0x0000 0000
Bits 22:18 FTx: Falling trigger event configuration bit of line x (x = 22 to 18)
0: Falling trigger disabled (for Event and Interrupt) for input line
1: Falling trigger enabled (for Event and Interrupt) for input line
Bit 17 Reserved, must be kept at reset value.
Bits 16:0 FTx: Falling trigger event configuration bit of line x (x = 16 to 0)
0: Falling trigger disabled (for Event and Interrupt) for input line
1: Falling trigger enabled (for Event and Interrupt) for input line
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res.
SWI
22
SWI
21
SWI
20
SWI
19
SWI
18
Res.
SWI
16
rw rw rw rw rw rw
1514131211109 8 765432 1 0
SWI
15
SWI
14
SWI
13
SWI
12
SWI
11
SWI
10
SWI
9
SWI
8
SWI
7
SWI
6
SWI
5
SWI
4
SWI
3
SWI
2
SWI
1
SWI
0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:23 Reserved, must be kept at reset value.
Bits 22: 18 SWIx: Software interrupt on line x (x = 22 o 18)
If the interrupt is enabled on this line in the EXTI_IMR, writing a '1' to this bit
when it is at '0' sets the corresponding pending bit in EXTI_PR resulting in an
interrupt request generation.
This bit is cleared by clearing the corresponding bit in the EXTI_PR register (by
writing a ‘1’ into the bit).
Bit 17 Reserved, must be kept at reset value.
Bits 16:0 SWIx: Software interrupt on line x (x = 16 to 0)
If the interrupt is enabled on this line in the EXTI_IMR, writing a '1' to this bit
when it is at '0' sets the corresponding pending bit in EXTI_PR resulting in an
interrupt request generation.
This bit is cleared by clearing the corresponding bit of EXTI_PR (by writing a ‘1’
into the bit).
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