DocID024597 Rev 3 521/1693
RM0351 Analog-to-digital converters (ADC)
540
16.5.12 ADC regular sequence register 2 (ADCx_SQR2)
Address offset: 0x34
Reset value: 0x0000 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. SQ9[4:0] Res. SQ8[4:0] Res. SQ7[4]
rw rw rw rw rw rw rw rw rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SQ7[3:0] Res. SQ6[4:0] Res. SQ5[4:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:29 Reserved, must be kept at reset value.
Bits 28:24 SQ9[4:0]: 9th conversion in regular sequence
These bits are written by software with the channel number (0..18) assigned as the 9th in the
regular conversion sequence.
Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no
regular conversion is ongoing).
Bit 23 Reserved, must be kept at reset value.
Bits 22:18 SQ8[4:0]: 8th conversion in regular sequence
These bits are written by software with the channel number (0..18) assigned as the 8th in the
regular conversion sequence
Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no
regular conversion is ongoing).
Bit 17 Reserved, must be kept at reset value.
Bits 16:12 SQ7[4:0]: 7th conversion in regular sequence
These bits are written by software with the channel number (0..18) assigned as the 7th in the
regular conversion sequence.
Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no
regular conversion is ongoing).
Bit 11 Reserved, must be kept at reset value.
Bits 10:6 SQ6[4:0]: 6th conversion in regular sequence
These bits are written by software with the channel number (0..18) assigned as the 6th in the
regular conversion sequence.
Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no
regular conversion is ongoing).
Bit 5 Reserved, must be kept at reset value.
Bits 4:0 SQ5[4:0]: 5th conversion in regular sequence
These bits are written by software with the channel number (0..18) assigned as the 5th in the
regular conversion sequence.
Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no
regular conversion is ongoing).