DocID024597 Rev 3 209/1693
RM0351 Reset and clock control (RCC)
253
6.4.6 PLLSAI2 configuration register (RCC_PLLSAI2CFGR)
Address offset: 0x14
Reset value: 0x0000 1000
Access: no wait state, word, half-word and byte access
This register is used to configure the PLLSAI2 clock outputs according to the formulas:
• f(VCOSAI2 clock) = f(PLL clock input) × (PLLSAI2N / PLLM)
• f(PLLSAI2_P) = f(VCOSAI2 clock) / PLLSAI2P
• f(PLLSAI2_R) = f(VCOSAI2 clock) / PLLSAI2R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. PLLSAI2R[1:0]
PLL
SAI2
REN
Res. Res. Res. Res. Res. Res.
PLL
SAI2P
PLL
SAI2
PEN
rw rw rw rw rw
1514131211109 8 7 654321 0
Res. PLLSAI2N[6:0] Res. Res. Res. Res. Res. Res. Res. Res.
rw rw rw rw rw rw rw
Bits 31:27 Reserved, must be kept at reset value.
Bits 26:25 PLLSAI2R[1:0]: PLLSAI2 division factor for PLLADC2CLK (ADC clock)
Set and cleared by software to control the frequency of the SAI2PLL output clock
PLLADC2CLK. This output can be selected as ADC clock. These bits can be written only if
SAI2PLL is disabled.
PLLADC2CLK output clock frequency = VCOSAI2 frequency / PLLSAI2R with PLLSAI2R =
2, 4, 6, or 8
00: PLLSAI2R = 2
01: PLLSAI2R = 4
10: PLLSAI2R = 6
11: PLLSAI2R = 8
Bit 24 PLLSAI2REN: PLLSAI2 PLLADC2CLK output enable
Set and reset by software to enable the PLLADC2CLK output of the SAI2PLL (used as clock
for ADC).
In order to save power, when the PLLADC2CLK output of the SAI2PLL is not used, the value
of PLLSAI2REN should be 0.
0: PLLADC2CLK output disable
1: PLLADC2CLK output enable
Bits 23:18 Reserved, must be kept at reset value.
Bit 17 PLLSAI2P: SAI1PLL division factor for PLLSAI2CLK (SAI1 or SAI2 clock).
Set and cleared by software to control the frequency of the SAI2PLL output clock
PLLSAI2CLK. This output can be selected for SAI1 or SAI2. These bits can be written only if
SAI2PLL is disabled.
PLLSAI2CLK output clock frequency = VCOSAI2 frequency / PLLSAI2P with PLLSAI2P =7,
or 17
0: PLLSAI2P = 7
1: PLLSAI2P = 17
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