ST STM32L4x6 User Manual

DocID024597 Rev 3 215/1693
RM0351 Reset and clock control (RCC)
253
6.4.9 Clock interrupt clear register (RCC_CICR)
Address offset: 0x20
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res.
1514131211109 8765432 1 0
Res. Res. Res. Res. Res. Res.
LSE
CSSC
CSSC
PLLSAI
2RDYC
PLL
SAI1
RDYC
PLL
RDYC
HSE
RDYC
HSI
RDYC
MSI
RDYC
LSE
RDYC
LSI
RDYC
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Bits 31:10 Reserved, must be kept at reset value.
Bit 9 LSECSSC: LSE Clock security system interrupt clear
This bit is set by software to clear the LSECSSF flag.
0: No effect
1: Clear LSECSSF flag
Bit 8 CSSC: Clock security system interrupt clear
This bit is set by software to clear the CSSF flag.
0: No effect
1: Clear CSSF flag
Bit 7 PLLSAI2RDYC: PLLSAI2 ready interrupt clear
This bit is set by software to clear the PLLSAI2RDYF flag.
0: No effect
1: Clear PLLSAI2RDYF flag
Bit 6 PLLSAI1RDYC: PLLSAI1 ready interrupt clear
This bit is set by software to clear the PLLSAI1RDYF flag.
0: No effect
1: Clear PLLSAI1RDYF flag
Bit 5 PLLRDYC: PLL ready interrupt clear
This bit is set by software to clear the PLLRDYF flag.
0: No effect
1: Clear PLLRDYF flag
Bit 4 HSERDYC: HSE ready interrupt clear
This bit is set by software to clear the HSERDYF flag.
0: No effect
1: Clear HSERDYF flag
Bit 3 HSIRDYC: HSI16 ready interrupt clear
This bit is set software to clear the HSIRDYF flag.
0: No effect
1: Clear HSIRDYF flag

ST STM32L4x6 Specifications

General

Brand	ST
Model	STM32L4x6
Category	Microcontrollers
Language	English