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RM0351 Flexible static memory controller (FSMC)
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14.6 NAND Flash controller
The FMC generates the appropriate signal timings to drive the following types of device:
• 8- and 16-bit NAND Flash memories
The NAND bank is configured through dedicated registers (Section 14.6.7). The
programmable memory parameters include access timings (shown in Table 76) and ECC
configuration.
Bits 3:0 ADDSET[3:0]: Address setup phase duration.
These bits are written by software to define the duration of the address setup phase in HCLK
cycles (refer to Figure 31 to Figure 43), used in asynchronous accesses:
0000: ADDSET phase duration = 0 × HCLK clock cycle
...
1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset)
Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash
clock period duration. In muxed mode, the minimum ADDSET value is 1.
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