DocID024597 Rev 3 607/1693
RM0351 Digital filter for sigma delta modulators (DFSDM)
657
21.3.3 DFSDM reset and clocks
DFSDM on-off control
The DFSDM interface is globally enabled by setting DFSDMEN=1 in the
DFSDM_CHCFG0R1 register. Once DFSDM is globally enabled, all input channels (y=0..7)
and digital filters DFSDMx (x=0..3) start to work if their enable bits are set (channel enable
bit CHEN in DFSDM_CHCFGyR1 and DFSDMx enable bit DFEN in DFSDMx_CR1).
Digital filter x DFSDMx (x=0..3) is enabled by setting DFEN=1 in the DFSDMx_CR1 register.
Once DFSDMx is enabled (DFEN=1), both Sinc
x
digital filter unit and integrator unit are
reinitialized.
By clearing DFEN, any conversion which may be in progress is immediately stopped and
DFSDMx is put into stop mode. All register settings remain unchanged except
DFSDMx_AWSR and DFSDMx_ISR (which are reset).
Channel y (y=0..7) is enabled by setting CHEN=1 in the DFSDM_CHCFGyR1 register.
Once the channel is enabled, it receives serial data from the external modulator or
parallel internal data sources (CPU/DMA wire from memory).
DFSDM must be globally disabled (by DFSDMEN=0 in DFSDM_CHCFG0R1) before
stopping the system clock to enter in the STOP mode of the device.
DFSDM clocks
The internal DFSDM clock f
DFSDMCLK
, which is used to drive the channel transceivers,
digital processing blocks (digital filter, integrator) and next additional blocks (analog
watchdog, short-circuit detector, extremes detector, control block) is generated by the RCC
block and is derived from the system clock SYSCLK (max. up to f
SYSCLK
= 80 MHz) or
peripheral clock PCLK2 (see DFSDMSEL bit description in Section 6.4.28: Peripherals
independent clock configuration register (RCC_CCIPR)). The DFSDM clock is automatically
stopped in stop mode (if DFEN = 0 for all DFSDMx, x=0..3).
The DFSDM serial channel transceivers can receive an external serial clock to sample an
external serial data stream. The internal DFSDM clock must be at least 4 times faster than
the external serial clock if standard SPI coding is used, and 6 times faster than the external
serial clock if Manchester coding is used.
DFSDM can provide one external output clock signal to drive external modulator(s) clock
input(s). It is provided on DFSDM_CKOUT pin. This output clock signal must be in the range
0 - 20 MHz and is derived from DFSDM clock or from audio clock (see CKOUTSRC bit in
DFSDM_CHCFG0R1 register) by programmable divider in the range 2 - 256 (CKOUTDIV in
DFSDM_CHCFG0R1 register). Audio clock source is SAI1 clock selected by SAI1SEL[1:0]
field in RCC configuration (see Section 6.4.28: Peripherals independent clock configuration
register (RCC_CCIPR)).
21.3.4 Serial channel transceivers
There are 8 multiplexed serial data channels which can be selected for conversion by each
filter or Analog watchdog or Short-circuit detector. Those serial transceivers receive data
stream from external modulator. Data stream can be sent in SPI format or Manchester
coded format (see SITP[1:0] bits in DFSDM_CHCFGyR1 register).
The channel is enabled for operation by setting CHEN=1 in DFSDM_CHCFGyR1 register.
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