DocID024597 Rev 3 625/1693
RM0351 Digital filter for sigma delta modulators (DFSDM)
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A modulator output is always assumed in a signed format (a data stream of zeros and
ones from a modulator represents values -1 and +1).
Signed data format in registers: Data is in a signed format in registers for final output data,
analog watchdog, extremes detector, offset correction. The msb of output data word
represents the sign of value (two’s complement format).
21.3.15 Launching conversions
Injected conversions can be launched using the following methods:
• Software: writing ‘1’ to JSWSTART in the DFSDMx_CR1 register.
• Trigger: JEXTSEL[2:0] selects the trigger signal while JEXTEN activates the trigger
and selects the active edge at the same time (see the DFSDMx_CR1 register).
• Synchronous with DFSDM0 if JSYNC=1: for DFSDMx (x>0), an injected conversion is
automatically launched when in DFSDM0; the injected conversion is started by
software (JSWSTART=1 in DFSDM0_CR2 register). Each injected conversion in
DFSDMx (x>0) is always executed according to its local configuration settings (JSCAN,
JCHG, etc.).
If the scan conversion is enabled (bit JSCAN=1) then, each time an injected conversion is
triggered, all of the selected channels in the injected group (JCHG[7:0] bits in
DFSDMx_JCHGR register) are converted sequentially, starting with the lowest channel
(channel 0, if selected).
If the scan conversion is disabled (bit JSCAN=0) then, each time an injected conversion is
triggered, only one of the selected channels in the injected group (JCHG[7:0] bits in
DFSDMx_JCHGR register) is converted and the channel selection is then moved to the next
selected channel. Writing to the JCHG[7:0] bits when JSCAN=0 sets the channel selection
to the lowest selected injected channel.
Only one injected conversion can be ongoing at a given time. Thus, any request to launch
an injected conversion is ignored if another request for an injected conversion has already
been issued but not yet completed.
Regular conversions can be launched using the following methods:
• Software: by writing ‘1’ to RSWSTART in the DFSDMx_CR1 register.
• Synchronous with DFSDM0 if RSYNC=1: for DFSDMx (x>0), a regular conversion is
automatically launched when in DFSDM0; a regular conversion is started by software
(RSWSTART=1 in DFSDM0_CR2 register). Each regular conversion in DFSDMx (x>0)
is always executed according to its local configuration settings (RCONT, RCH, etc.).
Only one regular conversion can be pending or ongoing at a given time. Thus, any request
to launch a regular conversion is ignored if another request for a regular conversion has
already been issued but not yet completed. A regular conversion can be pending if it was
interrupted by an injected conversion or if it was started while an injected conversion was in
progress. This pending regular conversion is then delayed and is performed when all
injected conversion are finished. Any delayed regular conversion is signalized by RPEND bit
in DFSDMx_RDATAR register.
21.3.16 Continuous and fast continuous modes
Setting RCONT in the DFSDMx_CR1 register causes regular conversions to execute in
continuous mode. RCONT=1 means that the channel selected by RCH[2:0] is converted
repeatedly after ‘1’ is written to RSWSTART.
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