DocID024597 Rev 3 305/1693
RM0351 Direct memory access controller (DMA)
318
Table 39. Summary of the DMA1 requests for each channel
Request.
number
Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7
0 ADC1 ADC2 ADC3 DFSDM0 DFSDM1 DFSDM2 DFSDM3
1 - SPI1_RX SPI1_TX SPI2_RX SPI2_TX SAI2_A SAI2_B
2 - USART3_TX USART3_RX USART1_TX USART1_RX USART2_RX USART2_TX
3 - I2C3_TX I2C3_RX I2C2_TX I2C2_RX I2C1_TX I2C1_RX
4 TIM2_CH3 TIM2_UP
TIM16_CH1
TIM16_UP
- TIM2_CH1
TIM16_CH1
TIM16_UP
TIM2_CH2
TIM2_CH4
5
TIM17_CH1
TIM17_UP
TIM3_CH3
TIM3_CH4
TIM3_UP
TIM7_UP.
DAC2
QUADSPI
TIM3_CH1
TIM3_TRIG
TIM17_CH1
TIM17_UP
6 TIM4_CH1 -
TIM6_UP
DAC1
TIM4_CH2 TIM4_CH3 - TIM4_UP
7 - TIM1_CH1 TIM1_CH2
TIM1_CH4
TIM1_TRIG
TIM1_COM
TIM15_CH1
TIM15_UP
TIM15_TRIG
TIM15_COM
TIM1_UP TIM1_CH3
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