ST STM32L4x6 User Manual

System configuration controller (SYSCFG) RM0351
282/1693 DocID024597 Rev 3
Note: Some of the I/O pins mentioned in the above register may not be available on small
packages.
8.2.7 SYSCFG SRAM2 control and status register (SYSCFG_SCSR)
Address offset: 0x18
System reset value: 0x0000 0000
Bits 6:4 EXTI13[2:0]: EXTI13 configuration bits
These bits are written by software to select the source input for the EXTI13 external
interrupt.
000: PA[13] pin
001: PB[13] pin
010: PC[13] pin
011: PD[13] pin
100: PE[13] pin
101: PF[13] pin
110: PG[13] pin
111: Reserved
Bit 3 Reserved, must be kept at reset value.
Bits 2:0 EXTI12[2:0]: EXTI12 configuration bits
These bits are written by software to select the source input for the EXTI12 external
interrupt.
000: PA[12] pin
001: PB[12] pin
010: PC[12] pin
011: PD[12] pin
100: PE[12] pin
101: PF[12] pin
110: PG[12] pin
111: Reserved
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res
1514131211109876543210
Res Res Res Res Res Res Res Res Res Res Res Res Res Res
SRAM2
BSY
SRAM2
ER
rrw
Bits 31:2 Reserved, must be kept at reset value
Bit 1 SRAM2BSY: SRAM2 busy by erase operation
0: No SRAM2 erase operation is on going.
1: SRAM2 erase operation is on going.
Bit 0 SRAM2ER: SRAM2 Erase
Setting this bit starts a hardware SRAM2 erase operation. This bit is
automatically cleared at the end of the SRAM2 erase operation.
Note: This bit is write-protected: setting this bit is possible only after the correct
key sequence is written in the SYSCFG_SKR register.

ST STM32L4x6 Specifications

General

Brand	ST
Model	STM32L4x6
Category	Microcontrollers
Language	English