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RM0351 Analog-to-digital converters (ADC)
540
Each channel can be sampled with a different sampling time which is programmable using
the SMP[2:0] bits in the ADCx_SMPR1 and ADCx_SMPR2 registers. It is therefore possible
to select among the following sampling time values:
• SMP = 000: 2.5 ADC clock cycles
• SMP = 001: 6.5 ADC clock cycles
• SMP = 010: 12.5 ADC clock cycles
• SMP = 011: 24.5 ADC clock cycles
• SMP = 100: 47.5 ADC clock cycles
• SMP = 101: 92.5 ADC clock cycles
• SMP = 110: 247.5 ADC clock cycles
• SMP = 111: 640.5 ADC clock cycles
The total conversion time is calculated as follows:
T
CONV
= Sampling time + 12.5 ADC clock cycles
Example:
With F
ADC_CLK
= 80 MHz and a sampling time of 2.5 ADC clock cycles:
T
CONV
= (2.5 + 12.5) ADC clock cycles = 15 ADC clock cycles = 187.5 ns (for fast
channels)
The ADC notifies the end of the sampling phase by setting the status bit EOSMP (only for
regular conversion).
Constraints on the sampling time for fast and slow channels
For each channel, SMP[2:0] bits must be programmed to respect a minimum sampling time
as specified in the ADC characteristics section of the datasheets.
I/O analog switches voltage booster
The I/O analog switches resistance increases when the V
DDA
voltage is too low. This
requires to have the sampling time adapted accordingly (cf datasheet for electrical
characteristics). This resistance can be minimized at low V
DDA
by enabling an internal
voltage booster with BOOSTEN bit in the SYSCFG_CFGR1 register.
16.3.13 Single conversion mode (CONT=0)
In Single conversion mode, the ADC performs once all the conversions of the channels.
This mode is started with the CONT bit at 0 by either:
• Setting the ADSTART bit in the ADCx_CR register (for a regular channel)
• Setting the JADSTART bit in the ADCx_CR register (for an injected channel)
• External hardware trigger event (for a regular or injected channel)
Inside the regular sequence, after each conversion is complete:
• The converted data are stored into the 16-bit ADCx_DR register
• The EOC (end of regular conversion) flag is set
• An interrupt is generated if the EOCIE bit is set
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