ST STM32L4x6 User Manual

Reset and clock control (RCC) RM0351
196/1693 DocID024597 Rev 3
6.4 RCC registers
6.4.1 Clock control register (RCC_CR)
Address offset: 0x00
Reset value: 0x0000 0063. HSEBYP is not affected by reset.
Access: no wait state, word, half-word and byte access
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res.
PLL
SAI2
RDY
PLL
SAI2
ON
PLL
SAI1
RDY
PLL
SAI1
ON
PLL
RDY
PLLON Res. Res. Res. Res.
CSS
ON
HSE
BYP
HSE
RDY
HSE
ON
r rw r rw r rw rs rw r rw
1514131211109 8765432 1 0
Res. Res. Res. Res.
HSI
ASFS
HSI
RDY
HSI
KERON
HSION MSIRANGE[3:0]
MSI
RGSEL
MSI
PLLEN
MSI
RDY
MSION
rw r rw rw rwrwrwrw rs rw r rw
Bits 31:30 Reserved, must be kept at reset value.
Bit 29 PLLSAI2RDY: SAI2 PLL clock ready flag
Set by hardware to indicate that the PLLSAI2 is locked.
0: PLLSAI2 unlocked
1: PLLSAI2 locked
Bit 28 PLLSAI2ON: SAI2 PLL enable
Set and cleared by software to enable PLLSAI2.
Cleared by hardware when entering Stop, Standby or Shutdown mode.
0: PLLSAI2 OFF
1: PLLSAI2 ON
Bit 27 PLLSAI1RDY: SAI1 PLL clock ready flag
Set by hardware to indicate that the PLLSAI1 is locked.
0: PLLSAI1 unlocked
1: PLLSAI1 locked
Bit 26 PLLSAI1ON: SAI1 PLL enable
Set and cleared by software to enable PLLSAI1.
Cleared by hardware when entering Stop, Standby or Shutdown mode.
0: PLLSAI1 OFF
1: PLLSAI1 ON
Bit 25 PLLRDY: Main PLL clock ready flag
Set by hardware to indicate that the main PLL is locked.
0: PLL unlocked
1: PLL locked
Bit 24 PLLON: Main PLL enable
Set and cleared by software to enable the main PLL.
Cleared by hardware when entering Stop, Standby or Shutdown mode. This bit cannot be
reset if the PLL clock is used as the system clock.
0: PLL OFF
1: PLL ON

ST STM32L4x6 Specifications

General

Brand	ST
Model	STM32L4x6
Category	Microcontrollers
Language	English