DocID024597 Rev 3 203/1693
RM0351 Reset and clock control (RCC)
253
6.4.4 PLL configuration register (RCC_PLLCFGR)
Address offset: 0x0C
Reset value: 0x0000 1000
Access: no wait state, word, half-word and byte access
This register is used to configure the PLL clock outputs according to the formulas:
• f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
• f(PLL_P) = f(VCO clock) / PLLP
• f(PLL_Q) = f(VCO clock) / PLLQ
• f(PLL_R) = f(VCO clock) / PLLR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res. Res. Res. Res. Res. PLLR[1:0]
PLL
REN
Res. PLLQ[1:0]
PLL
QEN
Res. Res. PLLP
PLL
PEN
rw rw rw rw rw rw rw rw
1514131211109 8 7 654321 0
Res. PLLN[7:0] Res. PLLM[2:0] Res. Res. PLLSRC[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:27 Reserved, must be kept at reset value.
Bits 26:25 PLLR[1:0]: Main PLL division factor for PLLCLK (system clock)
Set and cleared by software to control the frequency of the main PLL output clock PLLCLK.
This output can be selected as system clock. These bits can be written only if PLL is
disabled.
PLLCLK output clock frequency = VCO frequency / PLLR with PLLR = 2, 4, 6, or 8
00: PLLR = 2
01: PLLR = 4
10: PLLR = 6
11: PLLR = 8
Caution: The software has to set these bits correctly not to exceed 80 MHz on this
domain.
Bit 24 PLLREN: Main PLL PLLCLK output enable
Set and reset by software to enable the PLLCLK output of the main PLL (used as system
clock).
This bit cannot be written when PLLCLK output of the PLL is used as System Clock.
In order to save power, when the PLLCLK output of the PLL is not used, the value of
PLLREN should be 0.
0: PLLCLK output disable
1: PLLCLK output enable
Bit 23 Reserved, must be kept at reset value.
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