ST STM32L4x6 User Manual

DocID024597 Rev 3 283/1693
RM0351 System configuration controller (SYSCFG)
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8.2.8 SYSCFG configuration register 2 (SYSCFG_CFGR2)
Address offset: 0x1C
System reset value: 0x0000 0000
8.2.9 SYSCFG SRAM2 write protection register (SYSCFG_SWPR)
Address offset: 0x20
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res Res
1514131211109876543210
Res Res Res Res Res Res Res SPF Res Res Res Res ECCL PVDL SPL CLL
rc_w1 rsrsrsrs
Bits 31:9 Reserved, must be kept at reset value
Bit 8 SPF: SRAM2 parity error flag
This bit is set by hardware when an SRAM2 parity error is detected. It is cleared
by software by writing ‘1’.
0: No SRAM2 parity error detected
1: SRAM2 parity error detected
Bits 7:4 Reserved, must be kept at reset value
Bit 3 ECCL: ECC Lock
This bit is set by software and cleared only by a system reset. It can be used to
enable and lock the Flash ECC error connection to TIM1/8/15/16/17 Break input.
0: ECC error disconnected from TIM1/8/15/16/17 Break input.
1: ECC error connected to TIM1/8/15/16/17 Break input.
Bit 2 PVDL: PVD lock enable bit
This bit is set by software and cleared only by a system reset. It can be used to
enable and lock the PVD connection to TIM1/8/15/16/17 Break input, as well as
the PVDE and PLS[2:0] in the PWR_CR2 register.
0: PVD interrupt disconnected from TIM1/8/15/16/17 Break input. PVDE and
PLS[2:0] bits can be programmed by the application.
1: PVD interrupt connected to TIM1/8/15/16/17 Break input, PVDE and PLS[2:0]
bits are read only.
Bit 1 SPL: SRAM2 parity lock bit
This bit is set by software and cleared only by a system reset. It can be used to
enable and lock the SRAM2 parity error signal connection to TIM1/8/15/16/17
Break inputs.
0: SRAM2 parity error signal disconnected from TIM1/8/15/16/17 Break inputs
1: SRAM2 parity error signal connected to TIM1/8/15/16/17 Break inputs
Bit 0 CLL: Cortex
®
-M4 LOCKUP (Hardfault) output enable bit
This bit is set by software and cleared only by a system reset. It can be used to
enable and lock the connection of Cortex
®
-M4 LOCKUP (Hardfault) output to
TIM1/8/15/16/17 Break input
0: Cortex
®
-M4 LOCKUP output disconnected from TIM1/8/15/16/17 Break inputs
1: Cortex
®
-M4 LOCKUP output connected to TIM1/8/15/16/17 Break inputs

ST STM32L4x6 Specifications

General

Brand	ST
Model	STM32L4x6
Category	Microcontrollers
Language	English