Reset and clock control (RCC) RM0351
238/1693 DocID024597 Rev 3
Bit 25 CAN1SMEN: CAN1 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: CAN1 clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: CAN1 clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 24 Reserved, must be kept at reset value.
Bit 23 I2C3SMEN: I2C3 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: I2C3 clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: I2C3 clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 22 I2C2SMEN: I2C2 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: I2C2 clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: I2C2 clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 21 I2C1SMEN: I2C1 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: I2C1 clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: I2C1 clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 20 UART5SMEN: UART5 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: UART5 clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: UART5 clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 19 UART4SMEN: UART4 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: UART4 clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: UART4 clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 18 USART3SMEN: USART3 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: USART3 clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: USART3 clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 17 USART2SMEN: USART2 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: USART2 clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: USART2 clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 16 Reserved, must be kept at reset value.
Bit 15 SPI3SMEN: SPI3 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: SPI3 clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: SPI3 clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bit 14 SPI2SMEN: SPI2 clocks enable during Sleep and Stop modes
Set and cleared by software.
0: SPI2 clocks disabled by the clock gating
(1)
during Sleep and Stop modes
1: SPI2 clocks enabled by the clock gating
(1)
during Sleep and Stop modes
Bits 13:12 Reserved, must be kept at reset value.