DocID024597 Rev 3 685/1693
RM0351 Liquid crystal display controller (LCD)
690
Note: The data in this register can be updated any time, however the new values are applied only
at the beginning of the next frame (except for UDDIE, SOFIE that affect the device behavior
immediately).
The new value of CC[2:0] bits is also applied immediately but its effect on device is delayed
at the beginning of next frame by the voltage generator.
Reading this register obtains the last value written in the register and not the configuration
used to display the current frame.
Note: When BUFEN bit is set in the LCD_CR register, low resistor divider network is automatically
disabled whatever the HD or PON[2:0] bits configuration.
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