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DocID024597 Rev 3
709/1693
RM0351
Touch sensing
controller (TSC)
709
Refer to
Section
2.2.2 on page 67
for the register boundary addresses.
0x0048
TSC_IOG6CR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CNT[1
3:0]
Reset value
00000000000
000
0x004C
TSC_IOG7CR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CNT[1
3:0]
Reset value
00000000000
000
0x0050
TSC_IOG8CR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CNT[1
3:0]
Reset value
00000000000
000
T
able 139. TSC r
egister map and
reset values (con
tinued)
Offset
Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
708
710
Table of Contents
Default Chapter
2
Table of Contents
2
Documentation Conventions
61
List of Abbreviations for Registers
61
Glossary
61
Peripheral Availability
61
System and Memory Overview
62
System Architecture
62
S0: I-Bus
63
S1: D-Bus
63
Figure 1. System Architecture
63
S2: S-Bus
64
S3, S4: DMA-Bus
64
Busmatrix
64
Memory Organization
65
Introduction
65
Figure 2. Memory Map
66
Memory Map and Register Boundary Addresses
67
Table 1. Stm32L4X6 Memory Map and Peripheral Register Boundary Addresses
67
Bit Banding
71
Embedded SRAM
72
SRAM2 Parity Check
73
SRAM2 Write Protection
73
Table 2. SRAM2 Organization
73
Flash Memory Overview
74
SRAM2 Erase
74
SRAM2 Read Protection
74
Boot Configuration
75
Table 3. Boot Modes
75
Table 4. Memory Mapping Versus Boot Mode/Physical Remap
76
Embedded Flash Memory (FLASH)
78
FLASH Functional Description
78
Flash Memory Organization
78
Table 5. Flash Module - 1 MB Dual Bank Organization
79
Table 6. Flash Module - 512 KB Dual Bank Organization
80
Error Code Correction (ECC)
81
Table 7. Flash Module - 256 KB Dual Bank Organization
81
Read Access Latency
82
Table 8. Number of Wait States According to CPU Clock (HCLK) Frequency
82
Adaptive Real-Time Memory Accelerator (ART Accelerator™)
83
Figure 3. Sequential 16 Bits Instructions Execution
84
Flash Program and Erase Operations
85
Flash Main Memory Erase Sequences
86
Flash Main Memory Programming Sequences
87
Read-While-Write (RWW)
90
FLASH Main Features
78
Introduction
78
FLASH Option Bytes
92
Option Bytes Description
92
Table 9. Option Byte Format
92
Table 10. Option Byte Organization
92
Option Bytes Programming
97
FLASH Memory Protection
100
Read Protection (RDP)
100
Table 11. Flash Memory Read Protection Status
100
Table 12. Access Status Versus Protection Level and Execution Modes
102
Figure 4. Changing the Read Protection (RDP) Level
102
Proprietary Code Readout Protection (PCROP)
103
Write Protection (WRP)
104
FLASH Interrupts
105
Table 13. Flash Interrupt Request
105
FLASH Registers
106
Flash Access Control Register (FLASH_ACR)
106
Flash Power-Down Key Register (FLASH_PDKEYR)
107
Flash Key Register (FLASH_KEYR)
107
Flash Option Key Register (FLASH_OPTKEYR)
108
Flash Status Register (FLASH_SR)
108
Flash Control Register (FLASH_CR)
110
Flash ECC Register (FLASH_ECCR)
112
Flash Option Register (FLASH_OPTR)
113
Flash Bank 1 PCROP Start Address Register (FLASH_PCROP1SR)
114
Flash Bank 1 PCROP End Address Register (FLASH_PCROP1ER)
115
Flash Bank 1 WRP Area a Address Register (FLASH_WRP1AR)
115
Flash Bank 1 WRP Area B Address Register (FLASH_WRP1BR)
116
Flash Bank 2 PCROP Start Address Register (FLASH_PCROP2SR)
116
Flash Bank 2 PCROP End Address Register (FLASH_PCROP2ER)
117
Flash Bank 2 WRP Area a Address Register (FLASH_WRP2AR)
117
Flash Bank 2 WRP Area B Address Register (FLASH_WRP2BR)
118
FLASH Register Map
119
Table 14. Flash Interface - Register Map and Reset Values
119
Firewall (FW)
121
Firewall Main Features
121
Introduction
121
Firewall Functional Description
122
Firewall AMBA Bus Snoop
122
Functional Requirements
122
Figure 5. Stm32L4X6 Firewall Connection Schematics
122
Firewall Segments
123
Segment Accesses and Properties
124
Table 15. Segment Accesses According to the Firewall State
124
Firewall Initialization
125
Table 16. Segment Granularity and Area Ranges
125
Firewall States
126
Figure 6. Firewall Functional States
126
Firewall Registers
128
Code Segment Start Address (FW_CSSA)
128
Code Segment Length (FW_CSL)
128
Non-Volatile Data Segment Start Address (FW_NVDSSA)
129
Non-Volatile Data Segment Length (FW_NVDSL)
129
Volatile Data Segment Start Address (FW_VDSSA)
130
Volatile Data Segment Length (FW_VDSL)
130
Configuration Register (FW_CR)
131
Firewall Register Map
132
Table 17. Firewall Register Map and Reset Values
132
Power Control (PWR)
133
Power Supplies
133
Independent Analog Peripherals Supply
134
Figure 7. Power Supply Overview
134
Independent I/O Supply Rail
135
Independent USB Transceivers Supply
135
Independent LCD Supply
136
Battery Backup Domain
136
Voltage Regulator
137
Dynamic Voltage Scaling Management
138
Power Supply Supervisor
139
Power-On Reset (POR) / Power-Down Reset (PDR) / Brown-Out Reset
139
(Bor)
139
Programmable Voltage Detector (PVD)
139
Figure 8. Brown-Out Reset Waveform
139
Peripheral Voltage Monitoring (PVM)
140
Table 18. PVM Features
140
Figure 9. PVD Thresholds
140
Low-Power Modes
141
Figure 10. Low-Power Modes Possible Transitions
143
Table 19. Low-Power Mode Summary
144
Table 20. Functionalities Depending on the Working Mode
145
Run Mode
147
Low-Power Run Mode (LP Run)
148
Table 21. Low-Power Run
148
Low Power Modes
149
Low-Power Sleep Mode (LP Sleep)
150
Sleep Mode
150
Table 22. Sleep
150
Stop 0 Mode
151
Table 23. Low-Power Sleep
151
Stop 1 Mode
153
Table 24. Stop 0 Mode
153
Stop 2 Mode
154
Table 25. Stop 1 Mode
154
Table 26. Stop 2 Mode
156
Standby Mode
157
Table 27. Standby Mode
158
Shutdown Mode
159
Auto-Wakeup from Low-Power Mode
160
Table 28. Shutdown Mode
160
PWR Registers
161
Power Control Register 1 (PWR_CR1)
161
Power Control Register 2 (PWR_CR2)
162
Power Control Register 3 (PWR_CR3)
163
Power Control Register 4 (PWR_CR4)
164
Power Status Register 1 (PWR_SR1)
165
Power Status Register 2 (PWR_SR2)
166
Power Status Clear Register (PWR_SCR)
168
Power Port a Pull-Up Control Register (PWR_PUCRA)
168
Power Port a Pull-Down Control Register (PWR_PDCRA)
169
Power Port B Pull-Up Control Register (PWR_PUCRB)
169
Power Port B Pull-Down Control Register (PWR_PDCRB)
170
Power Port C Pull-Up Control Register (PWR_PUCRC)
170
Power Port C Pull-Down Control Register (PWR_PDCRC)
171
Power Port D Pull-Up Control Register (PWR_PUCRD)
171
Power Port D Pull-Down Control Register (PWR_PDCRD)
172
Power Port E Pull-Up Control Register (PWR_PUCRE)
172
Power Port E Pull-Down Control Register (PWR_PDCRE)
173
Power Port F Pull-Up Control Register (PWR_PUCRF)
173
Power Port F Pull-Down Control Register (PWR_PDCRF)
173
Power Port G Pull-Up Control Register (PWR_PUCRG)
174
Power Port G Pull-Down Control Register (PWR_PDCRG)
174
Power Port H Pull-Up Control Register (PWR_PUCRH)
175
Power Port H Pull-Down Control Register (PWR_PDCRH)
175
PWR Register Map and Reset Value Table
177
Table 29. PWR Register Map and Reset Values
177
Reset
179
Power Reset
179
System Reset
179
Backup Domain Reset
180
Figure 11. Simplified Diagram of the Reset Circuit
180
Reset and Clock Control (RCC)
179
Clocks
181
Figure 12. Clock Tree
184
Figure 13. HSE/ LSE Clock Sources
185
HSE Clock
185
HSI16 Clock
186
MSI Clock
187
LSE Clock
188
LSI Clock
189
Clock Security System (CSS)
190
Table 30. Clock Source Frequency
190
ADC Clock
191
Clock-Out Capability
192
Figure 14. Frequency Measurement with TIM15 in Capture Mode
192
Figure 15. Frequency Measurement with TIM16 in Capture Mode
193
Figure 16. Frequency Measurement with TIM17 in Capture Mode
193
Low-Power Modes
195
Clock Control Register (RCC_CR)
196
Internal Clock Sources Calibration Register (RCC_ICSCR)
199
Clock Configuration Register (RCC_CFGR)
200
PLL Configuration Register (RCC_PLLCFGR)
203
PLLSAI1 Configuration Register (RCC_PLLSAI1CFGR)
206
PLLSAI2 Configuration Register (RCC_PLLSAI2CFGR)
209
Clock Interrupt Enable Register (RCC_CIER)
211
Clock Interrupt Flag Register (RCC_CIFR)
213
Clock Interrupt Clear Register (RCC_CICR)
215
AHB1 Peripheral Reset Register (RCC_AHB1RSTR)
216
AHB2 Peripheral Reset Register (RCC_AHB2RSTR)
217
AHB3 Peripheral Reset Register (RCC_AHB3RSTR)
218
APB1 Peripheral Reset Register 1 (RCC_APB1RSTR1)
220
APB1 Peripheral Reset Register 2 (RCC_APB1RSTR2)
222
APB2 Peripheral Reset Register (RCC_APB2RSTR)
223
AHB1 Peripheral Clock Enable Register (RCC_AHB1ENR)
224
AHB2 Peripheral Clock Enable Register (RCC_AHB2ENR)
225
AHB3 Peripheral Clock Enable Register(RCC_AHB3ENR)
227
APB1 Peripheral Clock Enable Register 2 (RCC_APB1ENR2)
230
APB2 Peripheral Clock Enable Register (RCC_APB2ENR)
232
APB1 Peripheral Clocks Enable in Sleep and Stop Modes Register
237
Peripherals Independent Clock Configuration Register (RCC_CCIPR)
243
Backup Domain Control Register (RCC_BDCR)
246
Control/Status Register (RCC_CSR)
248
Table 31. RCC Register Map and Reset Values
250
Introduction
254
Figure 17. Basic Structure of an I/O Port Bit
255
Figure 18. Basic Structure of a Five-Volt Tolerant I/O Port Bit
255
Table 32. Port Bit Configuration Table
256
General-Purpose I/O (GPIO)
257
I/O Port Control Registers
258
GPIO Locking Mechanism
259
Figure 19. Input Floating/Pull Up/Pull down Configurations
260
Output Configuration
260
Alternate Function Configuration
261
Figure 20. Output Configuration
261
Figure 21. Alternate Function Configuration
262
Figure 22. High Impedance-Analog Configuration
262
Using the HSE or LSE Oscillator Pins as Gpios
263
GPIO Registers
264
GPIO Port Input Data Register (Gpiox_Idr) (X = A..H)
266
GPIO Port Bit Reset Register (Gpiox_Brr) (X =A..H)
269
Table 33. GPIO Register Map and Reset Values
271
SYSCFG Main Features
273
SYSCFG Configuration Register 1 (SYSCFG_CFGR1)
274
SYSCFG External Interrupt Configuration Register
276
SYSCFG External Interrupt Configuration Register
278
SYSCFG External Interrupt Configuration Register
279
SYSCFG SRAM2 Control and Status Register (SYSCFG_SCSR)
282
SYSCFG Configuration Register 2 (SYSCFG_CFGR2)
283
SYSCFG SRAM2 Key Register (SYSCFG_SKR)
284
Table 34. SYSCFG Register Map and Reset Values
285
Table 35. Stm32L4X6 Peripherals Interconnect Matrix
286
Introduction
286
Interconnection Details
287
From ADC (ADC1/ADC2/ADC3) to Timer (TIM1/TIM8)
289
From DFSDM to Timer (TIM1/TIM8/TIM15/TIM16/TIM17)
290
From RTC, COMP1, COMP2 to Low-Power Timer (LPTIM1/LPTIM2)
291
From USB to Timer (TIM2)
292
From System Errors to Timers (TIM1/TIM8/TIM15/TIM16/TIM17)
293
From Timers (TIM16/TIM17) to IRTIM
294
Introduction
295
Table 36. DMA Implementation
296
Figure 23. DMA Block Diagram
296
DMA Functional Description
297
DMA Channels
298
Table 37. Programmable Data Width & Endian Behavior (When Bits PINC = MINC = 1)
299
Programmable Data Width, Data Alignment and Endians
299
Table 38. DMA Interrupt Requests
301
Error Management
301
DMA Request Mapping
302
Figure 24. DMA1 Request Mapping
303
Figure 25. DMA2 Request Mapping
304
Table 39. Summary of the DMA1 Requests for each Channel
305
Table 40. Summary of the DMA2 Requests for each Channel
306
DMA Registers
307
DMA Interrupt Flag Clear Register (DMA_IFCR)
308
DMA Channel X Number of Data Register (Dma_Cndtrx) (X = 1
311
DMA Channel X Memory Address Register (Dma_Cmarx) (X = 1
312
DMA1 Channel Selection Register (DMA1_CSELR)
313
DMA2 Channel Selection Register (DMA2_CSELR)
315
Table 41. DMA Register Map and Reset Values
317
NVIC Main Features
319
Interrupt and Exception Vectors
320
Table 42. Stm32L4X6 Vector Table
320
Introduction
324
EXTI Block Diagram
325
Figure 26. Configurable Interrupt/Event Block Diagram
325
Peripherals Asynchronous Interrupts
326
Figure 27. External Interrupt/Event GPIO Mapping
327
Table 43. EXTI Lines Connections
327
Interrupt Mask Register 1 (EXTI_IMR1)
329
Rising Trigger Selection Register 1 (EXTI_RTSR1)
330
Software Interrupt Event Register 1 (EXTI_SWIER1)
331
Pending Register 1 (EXTI_PR1)
332
Event Mask Register 2 (EXTI_EMR2)
333
Falling Trigger Selection Register 2 (EXTI_FTSR2)
334
Pending Register 2 (EXTI_PR2)
335
EXTI Register Map
336
Table 44. Extended Interrupt/Event Controller Register Map and Reset Values
336
Cyclic Redundancy Check Calculation Unit (CRC)
337
CRC Functional Description
338
Figure 28. CRC Calculation Unit Block Diagram
338
CRC Registers
339
Independent Data Register (CRC_IDR)
340
Initial CRC Value (CRC_INIT)
341
Table 45. CRC Register Map and Reset Values
342
Flexible Static Memory Controller (FSMC)
343
Figure 29. FMC Block Diagram
344
AHB Interface
345
External Device Address Mapping
346
Figure 30. FMC Memory Banks
347
Table 46. NOR/PSRAM Bank Selection
347
Table 47. NOR/PSRAM External Memory Address
347
NAND Flash Memory Address Mapping
348
Table 48. NAND Memory Mapping and Timing Registers
348
Table 49. NAND Bank Selection
348
NOR Flash/Psram Controller
349
External Memory Interface Signals
350
Table 50. Programmable NOR/PSRAM Access Parameters
350
Table 51. Non-Multiplexed I/O nor Flash Memory
350
Table 52. 16-Bit Multiplexed I/O nor Flash Memory
351
Table 53. Non-Multiplexed I/Os PSRAM/SRAM
351
Table 54. 16-Bit Multiplexed I/O PSRAM
351
Table 55. nor Flash/Psram: Example of Supported Memories and Transactions
352
General Timing Rules
353
Figure 31. Mode1 Read Access Waveforms
354
NOR Flash/Psram Controller Asynchronous Transactions
354
Figure 32. Mode1 Write Access Waveforms
355
Table 56. Fmc_Bcrx Bit Fields
355
Table 57. Fmc_Btrx Bit Fields
356
Figure 33. Modea Read Access Waveforms
357
Figure 34. Modea Write Access Waveforms
357
Table 58. Fmc_Bcrx Bit Fields
358
Table 59. Fmc_Btrx Bit Fields
358
Figure 35. Mode2 and Mode B Read Access Waveforms
359
Table 60. Fmc_Bwtrx Bit Fields
359
Figure 36. Mode2 Write Access Waveforms
360
Figure 37. Modeb Write Access Waveforms
360
Table 61. Fmc_Bcrx Bit Fields
361
Table 62. Fmc_Btrx Bit Fields
361
Figure 38. Modec Read Access Waveforms
362
Table 63. Fmc_Bwtrx Bit Fields
362
Figure 39. Modec Write Access Waveforms
363
Table 64. Fmc_Bcrx Bit Fields
363
Table 65. Fmc_Btrx Bit Fields
364
Table 66. Fmc_Bwtrx Bit Fields
364
Figure 40. Moded Read Access Waveforms
365
Figure 41. Moded Write Access Waveforms
365
Table 67. Fmc_Bcrx Bit Fields
366
Table 68. Fmc_Btrx Bit Fields
366
Figure 42. Muxed Read Access Waveforms
367
Table 69. Fmc_Bwtrx Bit Fields
367
Figure 43. Muxed Write Access Waveforms
368
Table 70. Fmc_Bcrx Bit Fields
368
Table 71. Fmc_Btrx Bit Fields
369
Figure 44. Asynchronous Wait During a Read Access Waveforms
370
Figure 45. Asynchronous Wait During a Write Access Waveforms
371
Synchronous Transactions
371
Figure 46. Wait Configuration Waveforms
373
Figure 47. Synchronous Multiplexed Read Mode Waveforms - NOR, PSRAM (CRAM)
374
Table 72. Fmc_Bcrx Bit Fields
374
Table 73. Fmc_Btrx Bit Fields
375
Figure 48. Synchronous Multiplexed Write Mode Waveforms - PSRAM (CRAM)
376
Table 74. Fmc_Bcrx Bit Fields
376
Table 75. Fmc_Btrx Bit Fields
377
NOR/PSRAM Controller Registers
378
NAND Flash Controller
385
External Memory Interface Signals
386
Table 76. Programmable NAND Flash Access Parameters
386
Table 77. 8-Bit NAND Flash
386
Table 78. 16-Bit NAND Flash
387
NAND Flash Supported Memories and Transactions
388
Table 79. Supported Memories and Transactions
388
Figure 49. NAND Flash Controller Waveforms for Common Memory Access
389
NAND Flash Operations
389
Figure 50. Access to Non 'CE Don't Care' NAND-Flash
390
NAND Flash Prewait Functionality
390
In NAND Flash Memory
391
NAND Flashcontroller Registers
392
Table 80. ECC Result Relevant Bits
397
Table 81. FMC Register Map
398
Figure 51. QUADSPI Block Diagram
400
Introduction
400
Figure 52. an Example of a Read Command in Quad Mode
401
QUADSPI Command Sequence
401
QUADSPI Signal Interface Protocol Modes
403
Figure 53. an Example of a DDR Command in Quad Mode
404
QUADSPI Indirect Mode
404
QUADSPI Status Flag Polling Mode
406
QUADSPI Memory-Mapped Mode
407
QUADSPI Delayed Data Sampling
408
Sending the Instruction Only Once
410
Figure 54. Ncs When CKMODE = 0 (T = CLK Period)
411
QUADSPI Busy Bit and Abort Functionality
411
Figure 55. Ncs When CKMODE = 1 in SDR Mode (T = CLK Period)
412
Figure 56. Ncs When CKMODE = 1 in DDR Mode (T = CLK Period)
412
Figure 57. Ncs When CKMODE = 1 with an Abort (T = CLK Period)
412
Table 82. QUADSPI Interrupt Requests
413
QUADSPI Interrupts
413
QUADSPI Registers
414
QUADSPI Device Configuration Register (QUADSPI_DCR)
416
QUADSPI Status Register (QUADSPI_SR)
417
QUADSPI Flag Clear Register (QUADSPI_FCR)
418
QUADSPI Data Length Register (QUADSPI_DLR)
419
QUADSPI Address Register (QUADSPI_AR)
421
QUADSPI Data Register (QUADSPI_DR)
422
QUADSPI Polling Status Match Register (QUADSPI _PSMAR)
423
QUADSPI Low-Power Timeout Register (QUADSPI_LPTR)
424
Table 83. QUADSPI Register Map and Reset Values
425
Introduction
426
ADC Main Features
427
ADC Functional Description
429
Figure 58. ADC Block Diagram
429
Pins and Internal Signals
430
Clocks
431
Figure 59. ADC Clock Scheme
432
Table 84. ADC Internal Signals
430
Table 85. ADC Pins
430
Figure 60. ADC1 Connectivity
433
Figure 61. ADC2 Connectivity
434
Figure 62. ADC3 Connectivity
435
Slave AHB Interface
436
Calibration (ADCAL, ADCALDIF, Adcx_Calfact)
437
Figure 63. ADC Calibration
438
Figure 64. Updating the ADC Calibration Factor
439
Figure 65. Mixing Single-Ended and Differential Channels
439
ADC On-Off Control (ADEN, ADDIS, ADRDY)
440
Constraints When Writing the ADC Control Bits
441
Figure 66. Enabling / Disabling the ADC
441
Channel Selection (Sqrx, Jsqrx)
442
Single Conversion Mode (CONT=0)
443
Continuous Conversion Mode (CONT=1)
444
Starting Conversions (ADSTART, JADSTART)
445
Figure 67. Analog to Digital Conversion Time
446
Stopping an Ongoing Conversion (ADSTP, JADSTP)
446
Figure 68. Stopping Ongoing Regular Conversions
447
Figure 69. Stopping Ongoing Regular and Injected Conversions
447
Table 86. Configuring the Trigger Polarity for Regular External Triggers
448
Table 87. Configuring the Trigger Polarity for Injected External Triggers
448
Figure 70. Triggers Are Shared between ADC Master and ADC Slave
449
Table 88. ADC1, ADC2 and ADC3 - External Triggers for Regular Channels
449
Injected Channel Management
450
Table 89. ADC1, ADC2 and ADC3 - External Trigger for Injected Channels
450
Discontinuous Mode (DISCEN, DISCNUM, JDISCEN)
452
Figure 71. Injected Conversion Latency
452
Queue of Context for Injected Conversions
453
Figure 72. Example of JSQR Queue of Context (Sequence Change)
455
Figure 73. Example of JSQR Queue of Context (Trigger Change)
455
Figure 74. Example of JSQR Queue of Context with Overflow before Conversion
456
Figure 75. Example of JSQR Queue of Context with Overflow During Conversion
456
Figure 76. Example of JSQR Queue of Context with Empty Queue (Case JQM=0)
457
Figure 77. Example of JSQR Queue of Context with Empty Queue (Case JQM=1)
457
Figure 78. Flushing JSQR Queue of Context by Setting JADSTP=1 (JQM=0). Case When JADSTP Occurs During an Ongoing Conversion
458
Figure 79. Flushing JSQR Queue of Context by Setting JADSTP=1 (JQM=0). Case When JADSTP Occurs During an Ongoing Conversion and a New
458
Trigger Occurs
458
Figure 80. Flushing JSQR Queue of Context by Setting JADSTP=1 (JQM=0). Case When JADSTP Occurs Outside an Ongoing Conversion
459
Figure 81. Flushing JSQR Queue of Context by Setting JADSTP=1 (JQM=1)
459
Figure 82. Flushing JSQR Queue of Context by Setting ADDIS=1 (JQM=0)
460
Figure 83. Flushing JSQR Queue of Context by Setting ADDIS=1 (JQM=1)
460
Programmable Resolution (RES) - Fast Conversion Mode
461
Table 90. TSAR Timings Depending on Resolution
461
Figure 84. Single Conversions of a Sequence, Software Trigger
462
Figure 85. Continuous Conversion of a Sequence, Software Trigger
462
Data Management
463
Figure 86. Single Conversions of a Sequence, Hardware Trigger
463
Figure 87. Continuous Conversions of a Sequence, Hardware Trigger
463
Table 91. Offset Computation Versus Data Resolution
464
Figure 88. Right Alignment (Offset Disabled, Unsigned Value)
465
Figure 89. Right Alignment (Offset Enabled, Signed Value)
465
Figure 90. Left Alignment (Offset Disabled, Unsigned Value)
466
Figure 91. Left Alignment (Offset Enabled, Signed Value)
466
Figure 92. Example of Overrun (OVR)
467
Dynamic Low-Power Features
469
Figure 93. AUTODLY=1, Regular Conversion in Continuous Mode, Software Trigger
470
(Discen=0; Jdiscen=0)
471
Figure 94. AUTODLY=1, Regular HW Conversions Interrupted by Injected Conversions
471
(Discen=1, Jdiscen=1)
472
Figure 96. AUTODLY=1, Regular Continuous Conversions Interrupted by Injected Conversions
473
Figure 97. AUTODLY=1 in Auto- Injected Mode (JAUTO=1)
473
Analog Window Watchdog (AWD1EN, JAWD1EN, AWD1SGL AWD1CH, AWD2CH, AWD3CH, Awd_Htx, Awd_Ltx, Awdx)
474
Figure 98. Analog Watchdog's Guarded Area
474
Table 92. Analog Watchdog Channel Selection
474
Table 93. Analog Watchdog 1 Comparison
475
Table 94. Analog Watchdog 2 and 3 Comparison
475
Figure 99. Adcy_Awdx_Out Signal Generation (on All Regular Channels)
476
Figure 100. Adcy_Awdx_Out Signal Generation (Awdx Flag Not Cleared by SW)
477
Figure 101. Adcy_Awdx_Out Signal Generation (on a Single Regular Channel)
477
Figure 102. Adcy_Awdx_Out Signal Generation (on All Injected Channels)
477
Figure 103. 20-Bit to 16-Bit Result Truncation
478
Figure 104. Numerical Example with 5-Bits Shift and Rounding
478
Oversampler
478
Table 95. Maximum Output Results Versus N and M (Gray Cells Indicate Truncation)
479
Figure 105. Triggered Regular Oversampling Mode (TROVS Bit = 1)
480
Figure 106. Regular Oversampling Modes (4X Ratio)
481
Figure 107. Regular and Injected Oversampling Modes Used Simultaneously
482
Figure 108. Triggered Regular Oversampling with Injection
482
Dual ADC Modes
483
Figure 109. Oversampling in Auto-Injected Mode
483
Table 96. Oversampler Operating Modes Summary
483
Figure 110. Dual ADC Block Diagram (1)
485
Figure 111. Injected Simultaneous Mode on 4 Channels: Dual ADC Mode
486
Figure 112. Regular Simultaneous Mode on 16 Channels: Dual ADC Mode
488
Figure 113. Interleaved Mode on 1 Channel in Continuous Conversion Mode: Dual ADC Mode
490
Figure 114. Interleaved Mode on 1 Channel in Single Conversion Mode: Dual ADC Mode
490
Figure 115. Interleaved Conversion with Injection
491
Figure 116. Alternate Trigger: Injected Group of each ADC
492
Figure 117. Alternate Trigger: 4 Injected Channels (each ADC) in Discontinuous Mode
493
Figure 118. Alternate + Regular Simultaneous
494
Figure 119. Case of Trigger Occurring During Injected Conversion
494
Case 1: Master Interrupted First
495
Case 2: Slave Interrupted First
495
Figure 120. Interleaved Single Channel CH0 with Injected Sequence CH11, CH12
495
Figure 121. Two Interleaved Channels (CH1, CH2) with Injected Sequence CH11, CH12
495
Figure 122. Two Interleaved Channels (CH1, CH2) with Injected Sequence CH11, CH12
495
Figure 123. DMA Requests in Regular Simultaneous Mode When Mdma=0B00
496
Figure 124. DMA Requests in Regular Simultaneous Mode When Mdma=0B10
497
Figure 125. DMA Requests in Interleaved Mode When Mdma=0B10
497
Temperature Sensor
498
Figure 126. Temperature Sensor Channel Block Diagram
499
Figure 127. VBAT Channel Block Diagram
500
Figure 128. VREFINT Channel Block Diagram
501
Monitoring the Internal Voltage Reference
501
Table 97. ADC Interrupts Per each ADC
502
ADC Registers (for each ADC)
503
ADC Interrupt Enable Register (Adcx_Ier)
505
ADC Control Register (Adcx_Cr)
507
ADC Configuration Register (Adcx_Cfgr)
510
ADC Configuration Register 2 (Adcx_Cfgr2)
514
ADC Sample Time Register 1 (Adcx_Smpr1)
515
ADC Sample Time Register 2 (Adcx_Smpr2)
517
ADC Watchdog Threshold Register 2 (Adcx_Tr2)
518
ADC Watchdog Threshold Register 3 (Adcx_Tr3)
519
ADC Regular Sequence Register 1 (Adcx_Sqr1)
520
ADC Regular Sequence Register 2 (Adcx_Sqr2)
521
ADC Regular Sequence Register 3 (Adcx_Sqr3)
522
ADC Regular Sequence Register 4 (Adcx_Sqr4)
523
ADC Regular Data Register (Adcx_Dr)
524
ADC Injected Sequence Register (Adcx_Jsqr)
525
ADC Offset Register (Adcx_Ofry) (Y=1..4)
527
ADC Injected Data Register (Adcx_Jdry, Y= 1..4)
528
ADC Analog Watchdog 3 Configuration Register (Adcx_Awd3Cr)
529
ADC Calibration Factors (Adcx_Calfact)
530
ADC Common Registers
532
ADC Common Control Register (Adcx_Ccr)
534
Table 98. DELAY Bits Versus ADC Resolution
536
Table 99. ADC Global Register Map
537
ADC Common Regular Data Register for Dual Mode (Adcx_Cdr)
537
Table 100. ADC Register Map and Reset Values for each ADC
538
For Master ADC, 0X100 for Slave ADC)
538
Common Registers) Offset =0X300)
540
Introduction
541
DAC Functional Description
542
DAC Channel Enable
543
Table 102. DAC Pins
543
DAC Conversion
544
Figure 130. Data Registers in Single DAC Channel Mode
544
Figure 131. Data Registers in Dual DAC Channel Mode
544
DAC Output Voltage
545
Figure 132. Timing Diagram for Conversion with Trigger Disabled TEN = 0
545
Figure 133. DAC LFSR Register Calculation Algorithm
546
Noise Generation
546
Figure 134. DAC Conversion (SW Trigger Enabled) with LFSR Wave Generation
547
Figure 135. DAC Triangle Wave Generation
547
DAC Channel Modes
548
Figure 136. DAC Conversion (SW Trigger Enabled) with Triangle Wave Generation
548
Table 103. Sample and Refresh Timings
549
Figure 137. DAC Sample and Hold Mode Phases Diagram
550
DAC Channel Buffer Calibration
551
Table 104. Channel Output Modes Summary
551
Dual DAC Channel Conversion
553
Simultaneous Trigger with Different Triangle Generation
557
Table 105. Effect of Low-Power Modes on DAC
557
DAC Registers
559
DAC Software Trigger Register (DAC_SWTRGR)
562
DAC Channel1 Data Output Register (DAC_DOR1)
566
DAC Status Register (DAC_SR)
567
DAC Calibration Control Register (DAC_CCR)
568
DAC Sample and Hold Sample Time Register 1 (DAC_SHSR1)
569
DAC Sample and Hold Sample Time Register 2 (DAC_SHSR2)
570
DAC Sample and Hold Refresh Time Register (DAC_SHRR)
571
Table 106. DAC Register Map
572
Table 107. VREFBUF Buffer Modes
574
Voltage Reference Buffer (VREFBUF)
574
VREFBUF Calibration Control Register (VREFBUF_CCR)
575
Table 108. VREFBUF Register Map and Reset Values
576
Comparator (COMP)
577
COMP Functional Description
578
Figure 138. Comparators Block Diagram
578
Table 109. COMP1 Input Plus Assignment
578
Table 110. COMP1 Input Minus Assignment
578
COMP Reset and Clocks
579
Table 111. COMP2 Input Plus Assignment
579
Table 112. COMP2 Input Minus Assignment
579
Figure 139. Window Mode
580
Window Comparator
580
Figure 140. Comparator Hysteresis
581
Figure 141. Comparator Output Blanking
581
COMP Power and Speed Modes
582
Table 113. Comparator Behavior in the Low Power Modes
582
Table 114. Interrupt Control Bits
583
COMP Registers
584
Comparator 2 Control and Status Register (COMP2_CSR)
586
Table 115. COMP Register Map and Reset Values
588
Introduction
589
Table 116. Operational Amplifier Possible Connections
590
Initial Configuration
590
Figure 142. Standalone Mode: External Gain Setting Mode
591
OPAMP Modes
591
Figure 143. Follower Configuration
592
Figure 144. PGA Mode, Internal Gain Setting (X2/X4/X8/X16), Inverting Input Not Used
593
Figure 145. PGA Mode, Internal Gain Setting (X2/X4/X8/X16), Inverting Input Used for Filtering
594
Calibration
594
Table 117. Operating Modes and Calibration
595
Table 118. Effect of Low-Power Modes on the OPAMP
596
OPAMP Registers
597
OPAMP1 Offset Trimming Register in Normal Mode (OPAMP1_OTR)
598
OPAMP2 Control/Status Register (OPAMP2_CSR)
599
OPAMP2 Offset Trimming Register in Normal Mode (OPAMP2_OTR)
600
Table 119. OPAMP Register Map and Reset Values
602
Introduction
603
DFSDM Main Features
604
DFSDM Functional Description
605
Figure 146. Single DFSDM Block Diagram
605
DFSDM Pins and Internal Signals
606
Table 120. DFSDM External Pins
606
Table 121. DFSDM Internal Signals
606
Table 122. DFSDM Triggers Connection
606
DFSDM Reset and Clocks
607
Figure 147. Channel Transceiver Timing Diagrams
610
Figure 148. Clock Absence Timing Diagram for SPI
611
Figure 149. Clock Absence Timing Diagram for Manchester Coding
613
Figure 150. First Conversion for Manchester Coding (Manchester Synchronization)
614
Configuring the Input Serial Interface
616
Channel Selection
618
Figure 151. Dfsdm_Chdatinyr Registers Operation Modes and Assignment
618
Digital Filter Configuration
619
Figure 152. Example: Sinc3 Filter Response
619
For some FOSR Values
620
Integrator Unit
620
Output) for some IOSR Values and FOSR = 256 and Sinc3 Filter Type (Largest Data)
620
Table 123. Filter Maximum Output Resolution (Peak Data Values from Filter Output)
620
Table 124. Integrator Maximum Output Resolution
620
Short-Circuit Detector
622
Extremes Detector
623
Signed Data Format
624
Launching Conversions
625
Request Precedence
626
Power Optimization in Run Mode
627
Table 125. DFSDM Interrupt Requests
628
DFSDM DMA Transfer
629
Dfsdm_Awscdyr) (Y=0..7)
632
Dfsdmx Module Registers (X=0..3)
634
DFSDM Control Register 2 (Dfsdmx_Cr2)
637
DFSDM Interrupt and Status Register (Dfsdmx_Isr)
638
DFSDM Interrupt Flag Clear Register (Dfsdmx_Icr)
640
DFSDM Filter Control Register (Dfsdmx_Fcr)
641
DFSDM Data Register for Injected Group (Dfsdmx_Jdatar)
642
DFSDM Data Register for the Regular Channel (Dfsdmx_Rdatar)
643
DFSDM Analog Watchdog Low Threshold Register (Dfsdmx_Awltr)
644
DFSDM Analog Watchdog Status Register (Dfsdmx_Awsr)
645
DFSDM Extremes Detector Maximum Register (Dfsdmx_Exmax)
646
DFSDM Conversion Timer Register (Dfsdmx_Cnvtimr)
647
Table 126. DFSDM Register Map and Reset Values
648
Table 127. Dfsdmx Register Map and Reset Values
652
Liquid Crystal Display Controller (LCD)
658
LCD Main Features
659
Figure 153. LCD Controller Block Diagram
660
LCD Functional Description
660
Frequency Generator
661
Table 128. Example of Frame Rate Calculation
661
Common Driver
662
Figure 154. 1/3 Bias, 1/4 Duty
662
Figure 155. Static Duty Case 1
663
Figure 156. Static Duty Case 2
664
Figure 157. 1/2 Duty, 1/2 Bias
665
Segment Driver
665
Figure 158. 1/3 Duty, 1/3 Bias
666
Figure 159. 1/4 Duty, 1/3 Bias
667
Figure 160. 1/8 Duty, 1/4 Bias
668
Table 129. Blink Frequency
669
Voltage Generator and Contrast Control
669
Figure 161. VLCD Pin for 1/2 1/3 1/4 Bias
671
Figure 162. Deadtime
672
Double Buffer Memory
673
Table 130. Remapping Capability
674
Figure 163. SEG/COM Mux Feature Example
677
Figure 164. Flowchart Example
678
Flowchart
678
Table 131. LCD Behavior in Low-Power Modes
679
Table 132. LCD Interrupt Requests
679
LCD Registers
681
LCD Frame Control Register (LCD_FCR)
682
LCD Status Register (LCD_SR)
686
LCD Clear Register (LCD_CLR)
688
Table 133. LCD Register Map and Reset Values
689
Touch Sensing Controller (TSC)
691
Figure 165. TSC Block Diagram
692
TSC Functional Description
692
Figure 166. Surface Charge Transfer Analog I/O Group Structure
693
Figure 167. Sampling Capacitor Voltage Variation
694
Reset and Clocks
694
Figure 168. Charge Transfer Acquisition Sequence
695
Figure 169. Spread Spectrum Variation Principle
696
Spread Spectrum Feature
696
Table 135. Spread Spectrum Deviation Versus AHB Clock Frequency
696
Sampling Capacitor I/O and Channel I/O Mode Selection
697
Table 136. I/O State Depending on Its Mode and IODEF Bit Value
697
Acquisition Mode
698
Table 137. Effect of Low-Power Modes on TSC
699
Table 138. Interrupt Control Bits
699
Table 134. Acquisition Sequence Summary
694
TSC Registers
700
TSC Interrupt Enable Register (TSC_IER)
702
TSC Interrupt Clear Register (TSC_ICR)
703
TSC Interrupt Status Register (TSC_ISR)
704
TSC I/O Analog Switch Control Register (TSC_IOASCR)
705
TSC I/O Channel Control Register (TSC_IOCCRTSC_IOCCR)
706
Table 139. TSC Register Map and Reset Values
707
TSC I/O Group X Counter Register (Tsc_Iogxcr) (X = 1..8)
707
Figure 170. Block Diagram
710
Introduction
710
Operation
711
RNG Registers
712
RNG Data Register (RNG_DR)
713
Table 140. RNG Register Map and Reset Map
714
Introduction
715
Figure 171. AES Block Diagram
716
AES Functional Description
716
Encryption and Derivation Keys
717
AES Chaining Algorithms
718
Figure 172. ECB Encryption Mode
718
Cipher Block Chaining (CBC)
719
Figure 173. ECB Decryption Mode
719
Figure 174. CBC Mode Encryption
720
Figure 175. CBC Mode Decryption
720
Figure 176. Example of Suspend Mode Management
722
Counter Mode (CTR)
723
Figure 177. CTR Mode Encryption
723
Figure 178. CTR Mode Decryption
723
Figure 179. 32-Bit Counter + Nonce Organization
724
Galois Counter Mode (GCM)
724
AES Cipher Message Authentication Code Mode (CMAC)
727
Data Type
729
Figure 180. 128-Bit Block Construction According to the Data Type
730
Figure 181. 128-Bit Block Construction According to the Data Type (Continued)
731
Operating Modes
731
Figure 182. Mode 1: Encryption with 128-Bit Key Length
732
Figure 183. Mode 2: Key Derivation with 128-Bit Key Length
732
Figure 184. Mode 3: Decryption with 128-Bit Key Length
733
AES DMA Interface
734
Figure 185. Mode 4: Key Derivation and Decryption with 128-Bit Key Length
734
Error Flags
735
Figure 186. DMA Requests and Data Transfers During Input Phase (AES_IN)
735
Figure 187. DMA Requests During Output Phase (AES_OUT)
735
Table 141. Processing Time (in Clock Cycle)
736
Table 142. Processing Time (in Clock Cycle) for ECB, CBC and CTR
736
Table 143. Processing Time (in Clock Cycle) for GCM and CMAC
736
AES Interrupts
737
Table 144. AES Interrupt Requests
737
AES Registers
738
AES Status Register (AES_SR)
740
AES Data Input Register (AES_DINR)
742
AES Key Register 0 (AES_KEYR0) (LSB: Key [31:0])
743
AES Key Register 2 (AES_KEYR2) (Key [95:64])
744
AES Initialization Vector Register 1 (AES_IVR1) (IVR[63:32])
745
AES Initialization Vector Register 2 (AES_IVR2) (IVR[95:64])
746
AES Key Register 5 (AES_KEYR5) (Key[191:160])
747
Table 145. AES Register Map
749
TIM1/TIM8 Introduction
752
Figure 188. Advanced-Control Timer Block Diagram
753
TIM1/TIM8 Functional Description
754
Figure 189. Counter Timing Diagram with Prescaler Division Change from 1 to 2
755
Figure 190. Counter Timing Diagram with Prescaler Division Change from 1 to 4
755
Counter Modes
756
Figure 191. Counter Timing Diagram, Internal Clock Divided by 1
757
Figure 192. Counter Timing Diagram, Internal Clock Divided by 2
757
Figure 193. Counter Timing Diagram, Internal Clock Divided by 4
758
Figure 194. Counter Timing Diagram, Internal Clock Divided by N
758
Figure 195. Counter Timing Diagram, Update Event When ARPE=0 (Timx_Arr Not Preloaded)
759
Figure 196. Counter Timing Diagram, Update Event When ARPE=1 (Timx_Arr Preloaded)
759
Figure 197. Counter Timing Diagram, Internal Clock Divided by 1
761
Figure 198. Counter Timing Diagram, Internal Clock Divided by 2
761
Figure 199. Counter Timing Diagram, Internal Clock Divided by 4
762
Figure 200. Counter Timing Diagram, Internal Clock Divided by N
762
Figure 201. Counter Timing Diagram, Update Event When Repetition Counter Is Not Used
763
Figure 202. Counter Timing Diagram, Internal Clock Divided by 1, Timx_Arr = 0X6
764
Figure 203. Counter Timing Diagram, Internal Clock Divided by 2
765
Figure 204. Counter Timing Diagram, Internal Clock Divided by 4, Timx_Arr=0X36
765
Figure 205. Counter Timing Diagram, Internal Clock Divided by N
766
Figure 206. Counter Timing Diagram, Update Event with ARPE=1 (Counter Underflow)
766
Figure 207. Counter Timing Diagram, Update Event with ARPE=1 (Counter Overflow)
767
Repetition Counter
767
Figure 208. Update Rate Examples Depending on Mode and Timx_Rcr Register Settings
768
Figure 209. External Trigger Input Block
769
Figure 210. TIM1 ETR Input Circuitry
769
Figure 211. TIM8 ETR Input Circuitry
770
Clock Selection
771
Figure 212. Control Circuit in Normal Mode, Internal Clock Divided by 1
771
Figure 213. TI2 External Clock Connection Example
772
Figure 214. Control Circuit in External Clock Mode 1
773
Figure 215. External Trigger Input Block
773
Figure 216. Control Circuit in External Clock Mode 2
774
Capture/Compare Channels
775
Figure 217. Capture/Compare Channel (Example: Channel 1 Input Stage)
775
Figure 218. Capture/Compare Channel 1 Main Circuit
776
Figure 219. Output Stage of Capture/Compare Channel (Channel 1, Idem Ch. 2 and 3)
776
Figure 220. Output Stage of Capture/Compare Channel (Channel 4)
777
Figure 221. Output Stage of Capture/Compare Channel (Channel 5, Idem Ch. 6)
777
Input Capture Mode
778
Figure 222. PWM Input Mode Timing
779
Output Compare Mode
780
Figure 223. Output Compare Mode, Toggle on OC1
781
PWM Mode
781
Figure 224. Edge-Aligned PWM Waveforms (ARR=8)
782
Figure 225. Center-Aligned PWM Waveforms (ARR=8)
783
Asymmetric PWM Mode
784
Combined PWM Mode
785
Figure 226. Generation of 2 Phase-Shifted PWM Signals with 50% Duty Cycle
785
Combined 3-Phase PWM Mode
786
Figure 227. Combined PWM Mode on Channel 1 and 3
786
Complementary Outputs and Dead-Time Insertion
787
Figure 228. 3-Phase Combined PWM Signals with Multiple Trigger Pulses Per Period
787
Figure 229. Complementary Output with Dead-Time Insertion
788
Figure 230. Dead-Time Waveforms with Delay Greater than the Negative Pulse
788
Figure 231. Dead-Time Waveforms with Delay Greater than the Positive Pulse
789
Using the Break Function
789
Figure 232. Break and Break2 Circuitry Overview
791
Figure 233. Various Output Behavior in Response to a Break Event on BRK (OSSI = 1)
793
Figure 234. PWM Output State Following BRK and BRK2 Pins Assertion (OSSI=1)
794
Table 146. Behavior of Timer Outputs Versus BRK/BRK2 Inputs
794
Bidirectional Break Inputs
795
Figure 235. PWM Output State Following BRK Assertion (OSSI=0)
795
Figure 236. Output Redirection
795
Figure 237. Clearing Timx Ocxref
796
Figure 238. 6-Step Generation, COM Example (OSSR=1)
797
Step PWM Generation
797
Figure 239. Example of One Pulse Mode
798
Retriggerable One Pulse Mode (OPM)
799
Encoder Interface Mode
800
Figure 240. Retriggerable One Pulse Mode
800
Figure 241. Example of Counter Operation in Encoder Interface Mode
801
Table 147. Counting Direction Versus Encoder Signals
801
Figure 242. Example of Encoder Interface Mode with TI1FP1 Polarity Inverted
802
UIF Bit Remapping
802
Figure 243. Measuring Time Interval between Edges on 3 Signals
803
Timer Input XOR Function
803
Figure 244. Example of Hall Sensor Interface
805
Figure 245. Control Circuit in Reset Mode
806
Timer Synchronization
806
Figure 246. Control Circuit in Gated Mode
807
Figure 247. Control Circuit in Trigger Mode
808
Figure 248. Control Circuit in External Clock Mode 2 + Trigger Mode
809
ADC Synchronization
810
Debug Mode
811
TIM1/TIM8 Registers
812
TIM1/TIM8 Control Register 2 (Timx_Cr2)
813
TIM1/TIM8 Slave Mode Control Register (Timx_Smcr)
816
Table 148. Timx Internal Trigger Connection
818
TIM1/TIM8 Dma/Interrupt Enable Register (Timx_Dier)
819
TIM1/TIM8 Status Register (Timx_Sr)
820
TIM1/TIM8 Event Generation Register (Timx_Egr)
822
TIM1/TIM8 Capture/Compare Mode Register 1 (Timx_Ccmr1)
823
TIM1/TIM8 Capture/Compare Mode Register 2 (Timx_Ccmr2)
828
TIM1/TIM8 Capture/Compare Enable Register (Timx_Ccer)
829
Table 149. Output Control Bits for Complementary Ocx and Ocxn Channels with Break Feature
832
TIM1/TIM8 Counter (Timx_Cnt)
833
TIM1/TIM8 Repetition Counter Register (Timx_Rcr)
834
TIM1/TIM8 Capture/Compare Register 2 (Timx_Ccr2)
835
TIM1/TIM8 Capture/Compare Register 4 (Timx_Ccr4)
836
TIM1/TIM8 DMA Control Register (Timx_Dcr)
840
TIM1/TIM8 DMA Address for Full Transfer (Timx_Dmar)
841
TIM8 Option Register 1 (TIM8_OR1)
842
TIM1/TIM8 Capture/Compare Mode Register 3 (Timx_Ccmr3)
843
TIM1/TIM8 Capture/Compare Register 6 (Timx_Ccr6)
845
TIM1 Option Register 3 (TIM1_OR3)
847
TIM8 Option Register 2 (TIM8_OR2)
848
TIM8 Option Register 3 (TIM8_OR3)
850
Table 150. TIM1 Register Map and Reset Values
851
Table 151. TIM8 Register Map and Reset Values
854
TIM2/TIM3/TIM4/TIM5 Introduction
857
Figure 249. General-Purpose Timer Block Diagram
858
TIM2/TIM3/TIM4/TIM5 Functional Description
859
Figure 250. Counter Timing Diagram with Prescaler Division Change from 1 to 2
860
Figure 251. Counter Timing Diagram with Prescaler Division Change from 1 to 4
860
Counter Modes
861
Figure 252. Counter Timing Diagram, Internal Clock Divided by 1
861
Figure 253. Counter Timing Diagram, Internal Clock Divided by 2
862
Figure 254. Counter Timing Diagram, Internal Clock Divided by 4
862
Figure 255. Counter Timing Diagram, Internal Clock Divided by N
863
Figure 256. Counter Timing Diagram, Update Event When ARPE=0 (Timx_Arr Not Preloaded)
863
Figure 257. Counter Timing Diagram, Update Event When ARPE=1 (Timx_Arr Preloaded)
864
Figure 258. Counter Timing Diagram, Internal Clock Divided by 1
865
Figure 259. Counter Timing Diagram, Internal Clock Divided by 2
865
Figure 260. Counter Timing Diagram, Internal Clock Divided by 4
866
Figure 261. Counter Timing Diagram, Internal Clock Divided by N
866
Figure 262. Counter Timing Diagram, Update Event When Repetition Counter
867
Is Not Used
867
Figure 263. Counter Timing Diagram, Internal Clock Divided by 1, Timx_Arr=0X6
868
Figure 264. Counter Timing Diagram, Internal Clock Divided by 2
869
Figure 265. Counter Timing Diagram, Internal Clock Divided by 4, Timx_Arr=0X36
869
Figure 266. Counter Timing Diagram, Internal Clock Divided by N
870
Figure 267. Counter Timing Diagram, Update Event with ARPE=1 (Counter Underflow)
870
Clock Selection
871
Figure 268. Counter Timing Diagram, Update Event with ARPE=1 (Counter Overflow)
871
Figure 269. Control Circuit in Normal Mode, Internal Clock Divided by 1
872
Figure 270. TI2 External Clock Connection Example
872
Figure 271. Control Circuit in External Clock Mode 1
873
Figure 272. External Trigger Input Block
874
Capture/Compare Channels
875
Figure 273. Control Circuit in External Clock Mode 2
875
Figure 274. Capture/Compare Channel (Example: Channel 1 Input Stage)
876
Figure 275. Capture/Compare Channel 1 Main Circuit
876
Figure 276. Output Stage of Capture/Compare Channel (Channel 1)
877
Input Capture Mode
877
Figure 277. PWM Input Mode Timing
879
Forced Output Mode
880
Figure 278. Output Compare Mode, Toggle on OC1
881
PWM Mode
881
Figure 279. Edge-Aligned PWM Waveforms (ARR=8)
882
Figure 280. Center-Aligned PWM Waveforms (ARR=8)
884
Asymmetric PWM Mode
885
Figure 281. Generation of 2 Phase-Shifted PWM Signals with 50% Duty Cycle
885
Clearing the Ocxref Signal on an External Event
886
Figure 282. Combined PWM Mode on Channels 1 and 3
886
Figure 283. Clearing Timx Ocxref
887
Figure 284. Example of One-Pulse Mode
888
Retriggerable One Pulse Mode (OPM)
889
Encoder Interface Mode
890
Figure 285. Retriggerable One Pulse Mode
890
Figure 286. Example of Counter Operation in Encoder Interface Mode
891
Table 152. Counting Direction Versus Encoder Signals
891
Figure 287. Example of Encoder Interface Mode with TI1FP1 Polarity Inverted
892
UIF Bit Remapping
892
Figure 288. Control Circuit in Reset Mode
893
Timers and External Trigger Synchronization
893
Figure 289. Control Circuit in Gated Mode
894
Figure 290. Control Circuit in Trigger Mode
895
Figure 291. Control Circuit in External Clock Mode 2 + Trigger Mode
896
Figure 292. Master/Slave Timer Example
896
Timer Synchronization
896
Figure 293. Gating TIM2 with OC1REF of TIM3
897
Figure 294. Gating TIM2 with Enable of TIM3
898
Figure 295. Triggering TIM2 with Update of TIM3
899
Figure 296. Triggering TIM2 with Enable of TIM3
899
DMA Burst Mode
900
Figure 297. Triggering TIM3 and TIM2 with TIM3 TI1 Input
900
Debug Mode
901
TIM2/TIM3/TIM4/TIM5 Registers
902
Timx Control Register 2 (Timx_Cr2)
904
Timx Slave Mode Control Register (Timx_Smcr)
905
Table 153. Timx Internal Trigger Connection
907
Timx Dma/Interrupt Enable Register (Timx_Dier)
909
Timx Status Register (Timx_Sr)
910
Timx Event Generation Register (Timx_Egr)
912
Timx Capture/Compare Mode Register 1 (Timx_Ccmr1)
913
Timx Capture/Compare Mode Register 2 (Timx_Ccmr2)
917
Timx Capture/Compare Enable Register (Timx_Ccer)
918
Table 154. Output Control Bit for Standard Ocx Channels
920
Timx Counter (Timx_Cnt)
920
Timx Prescaler (Timx_Psc)
921
Timx Capture/Compare Register 2 (Timx_Ccr2)
922
Timx Capture/Compare Register 4 (Timx_Ccr4)
923
Timx DMA Control Register (Timx_Dcr)
924
TIM2 Option Register 1 (TIM2_OR1)
925
TIM3 Option Register 2 (TIM3_OR2)
926
Table 155. TIM2/TIM3/TIM4/TIM5 Register Map and Reset Values
927
Timx Register Map
927
TIM15/16/17 Introduction
930
TIM16 and TIM17 Main Features
931
Figure 298. TIM15 Block Diagram
932
Figure 299. TIM16 and TIM17 Block Diagram
933
TIM15/16/17 Functional Description
934
Figure 300. Counter Timing Diagram with Prescaler Division Change from 1 to 2
935
Figure 301. Counter Timing Diagram with Prescaler Division Change from 1 to 4
935
Counter Modes
936
Figure 302. Counter Timing Diagram, Internal Clock Divided by 1
937
Figure 303. Counter Timing Diagram, Internal Clock Divided by 2
937
Figure 304. Counter Timing Diagram, Internal Clock Divided by 4
938
Figure 305. Counter Timing Diagram, Internal Clock Divided by N
938
Preloaded)
939
Repetition Counter
940
Clock Selection
941
Figure 308. Update Rate Examples Depending on Mode and Timx_Rcr Register Settings
941
Figure 309. Control Circuit in Normal Mode, Internal Clock Divided by 1
942
Figure 310. TI2 External Clock Connection Example
942
Capture/Compare Channels
943
Figure 311. Control Circuit in External Clock Mode 1
943
Figure 312. Capture/Compare Channel (Example: Channel 1 Input Stage)
944
Figure 313. Capture/Compare Channel 1 Main Circuit
944
Figure 314. Output Stage of Capture/Compare Channel (Channel 1)
945
Figure 315. Output Stage of Capture/Compare Channel (Channel 2 for TIM15)
945
Input Capture Mode
946
Figure 316. PWM Input Mode Timing
947
PWM Input Mode (Only for TIM15)
947
Forced Output Mode
948
Figure 317. Output Compare Mode, Toggle on OC1
949
PWM Mode
949
Combined PWM Mode (TIM15 Only)
950
Figure 318. Edge-Aligned PWM Waveforms (ARR=8)
950
Figure 319. Combined PWM Mode on Channel 1 and 2
951
Complementary Outputs and Dead-Time Insertion
952
Figure 320. Complementary Output with Dead-Time Insertion
952
Figure 321. Dead-Time Waveforms with Delay Greater than the Negative Pulse
953
Figure 322. Dead-Time Waveforms with Delay Greater than the Positive Pulse
953
Using the Break Function
954
Figure 323. Break Circuitry Overview
955
Figure 324. Output Behavior in Response to a Break
957
Figure 325. Example of One Pulse Mode
958
UIF Bit Remapping
959
Figure 326. Measuring Time Interval between Edges on 2 Signals
960
Timer Input XOR Function (TIM15 Only)
960
External Trigger Synchronization (TIM15 Only)
961
Figure 327. Control Circuit in Reset Mode
961
Figure 328. Control Circuit in Gated Mode
962
Figure 329. Control Circuit in Trigger Mode
963
Slave Mode: Combined Reset + Trigger Mode
963
Debug Mode
964
TIM15 Registers
965
TIM15 Control Register 2 (TIM15_CR2)
966
TIM15 Slave Mode Control Register (TIM15_SMCR)
968
Table 156. Timx Internal Trigger Connection
969
TIM15 Dma/Interrupt Enable Register (TIM15_DIER)
969
TIM15 Status Register (TIM15_SR)
970
TIM15 Event Generation Register (TIM15_EGR)
972
TIM15 Capture/Compare Mode Register 1 (TIM15_CCMR1)
973
TIM15 Capture/Compare Enable Register (TIM15_CCER)
976
Table 157. Output Control Bits for Complementary Ocx and Ocxn Channels with Break Feature
978
TIM15 Counter (TIM15_CNT)
979
TIM15 Repetition Counter Register (TIM15_RCR)
980
TIM15 Capture/Compare Register 2 (TIM15_CCR2)
981
TIM15 DMA Control Register (TIM15_DCR)
983
TIM15 Option Register 1 (TIM15_OR1)
984
Table 158. TIM15 Register Map and Reset Values
986
TIM16&TIM17 Registers
989
TIM16&TIM17 Control Register 2 (Timx_Cr2)
990
TIM16&TIM17 Dma/Interrupt Enable Register (Timx_Dier)
991
TIM16&TIM17 Status Register (Timx_Sr)
992
TIM16&TIM17 Event Generation Register (Timx_Egr)
993
TIM16&TIM17 Capture/Compare Mode Register 1 (Timx_Ccmr1)
994
TIM16&TIM17 Capture/Compare Enable Register (Timx_Ccer)
996
Table 159. Output Control Bits for Complementary Ocx and Ocxn Channels with Break Feature
998
TIM16&TIM17 Counter (Timx_Cnt)
998
TIM16&TIM17 Prescaler (Timx_Psc)
999
TIM16&TIM17 Repetition Counter Register (Timx_Rcr)
1000
TIM16&TIM17 Break and Dead-Time Register (Timx_Bdtr)
1001
TIM16&TIM17 DMA Control Register (Timx_Dcr)
1003
TIM16 Option Register 2 (TIM16_OR2)
1004
TIM17 Option Register 1 (TIM17_OR1)
1005
TIM17 Option Register 2 (TIM17_OR2)
1006
Table 160. TIM16&TIM17 Register Map and Reset Values
1008
Figure 330. Basic Timer Block Diagram
1010
TIM6/TIM7 Introduction
1010
TIM6/TIM7 Functional Description
1011
Figure 331. Counter Timing Diagram with Prescaler Division Change from 1 to 2
1012
Figure 332. Counter Timing Diagram with Prescaler Division Change from 1 to 4
1012
Counting Mode
1013
Figure 333. Counter Timing Diagram, Internal Clock Divided by 1
1013
Figure 334. Counter Timing Diagram, Internal Clock Divided by 2
1014
Figure 335. Counter Timing Diagram, Internal Clock Divided by 4
1014
Figure 336. Counter Timing Diagram, Internal Clock Divided by N
1015
Preloaded)
1015
Preloaded)
1016
UIF Bit Remapping
1016
Debug Mode
1017
Figure 339. Control Circuit in Normal Mode, Internal Clock Divided by 1
1017
TIM6/TIM7 Control Register 2 (Timx_Cr2)
1019
TIM6/TIM7 Status Register (Timx_Sr)
1020
TIM6/TIM7 Prescaler (Timx_Psc)
1021
Table 161. TIM6/TIM7 Register Map and Reset Values
1022
Introduction
1023
Table 162. Stm32L4Xx LPTIM Features
1023
Figure 340. Low-Power Timer Block Diagram
1024
LPTIM Functional Description
1024
Figure 341. Glitch Filter Timing Diagram
1025
Prescaler
1026
Table 163. Prescaler Division Ratios
1026
And Set-Once Mode Activated (WAVE Bit Is Set)
1027
Figure 342. LPTIM Output Waveform, Single Counting Mode Configuration
1027
Figure 343. LPTIM Output Waveform, Single Counting Mode Configuration
1027
Operating Mode
1027
Figure 344. LPTIM Output Waveform, Continuous Counting Mode Configuration
1028
Timeout Function
1028
Waveform Generation
1029
Figure 345. Waveform Generation
1030
Register Update
1030
Counter Mode
1031
Table 164. Encoder Counting Scenarios
1032
Figure 346. Encoder Mode Counting Sequence
1033
Table 165. Effect of Low-Power Modes on the LPTIM
1033
LPTIM Interrupts
1034
LPTIM Registers
1035
LPTIM Interrupt Clear Register (Lptimx_Icr)
1036
LPTIM Interrupt Enable Register (Lptimx_Ier)
1037
LPTIM Configuration Register (Lptimx_Cfgr)
1038
Table 166. LPTIM External Trigger Connection
1040
LPTIM Control Register (Lptimx_Cr)
1041
LPTIM Compare Register (Lptimx_Cmp)
1042
LPTIM Counter Register (Lptimx_Cnt)
1043
Table 167. LPTIM Register Map and Reset Values
1045
Figure 347. IR Internal Hardware Connections with TIM16 and TIM17
1046
Infrared Interface (IRTIM)
1046
Figure 348. Independent Watchdog Block Diagram
1047
Introduction
1047
Window Option
1048
Low-Power Freeze
1049
IWDG Registers
1050
Prescaler Register (IWDG_PR)
1051
Reload Register (IWDG_RLR)
1052
Status Register (IWDG_SR)
1053
Window Register (IWDG_WINR)
1054
Table 168. IWDG Register Map and Reset Values
1055
System Window Watchdog (WWDG)
1056
Figure 349. Watchdog Block Diagram
1057
Enabling the Watchdog
1057
Figure 350. Window Watchdog Timing Diagram
1058
How to Program the Watchdog Timeout
1058
Debug Mode
1059
WWDG Registers
1060
Configuration Register (WWDG_CFR)
1061
Table 169. WWDG Register Map and Reset Values
1062
Real-Time Clock (RTC)
1063
RTC Main Features
1064
RTC Functional Description
1065
Gpios Controlled by the RTC
1066
Table 170. RTC Pin PC13 Configuration
1066
Clock and Prescalers
1067
Table 171. RTC_OUT Mapping
1067
Real-Time Clock and Calendar
1068
Programmable Alarms
1069
RTC Initialization and Configuration
1070
Reading the Calendar
1071
Resetting the RTC
1072
RTC Synchronization
1073
RTC Smooth Digital Calibration
1074
Time-Stamp Function
1076
Tamper Detection
1077
Calibration Clock Output
1079
Table 172. Effect of Low-Power Modes on RTC
1079
RTC Interrupts
1080
RTC Registers
1081
RTC Date Register (RTC_DR)
1082
RTC Control Register (RTC_CR)
1083
RTC Initialization and Status Register (RTC_ISR)
1086
RTC Prescaler Register (RTC_PRER)
1089
RTC Wakeup Timer Register (RTC_WUTR)
1090
RTC Alarm a Register (RTC_ALRMAR)
1091
RTC Alarm B Register (RTC_ALRMBR)
1092
RTC Write Protection Register (RTC_WPR)
1093
RTC Shift Control Register (RTC_SHIFTR)
1094
RTC Timestamp Time Register (RTC_TSTR)
1095
RTC Timestamp Date Register (RTC_TSDR)
1096
RTC Time-Stamp Sub Second Register (RTC_TSSSR)
1097
RTC Calibration Register (RTC_CALR)
1098
RTC Tamper Configuration Register (RTC_TAMPCR)
1099
RTC Alarm a Sub Second Register (RTC_ALRMASSR)
1102
RTC Alarm B Sub Second Register (RTC_ALRMBSSR)
1103
RTC Option Register (RTC_OR)
1104
Table 174. RTC Register Map and Reset Values
1105
Introduction
1107
Table 175. Stm32L4X6 I2C Implementation
1108
Figure 352. I2C Block Diagram
1109
I2C Clock Requirements
1110
Figure 353. I2C Bus Protocol
1111
Table 176. Comparison of Analog Vs. Digital Filters
1112
I2C Initialization
1112
Figure 354. Setup and Hold Timings
1113
Figure 355. I2C Initialization Flowchart
1116
Software Reset
1116
Figure 356. Data Reception
1117
Data Transfer
1117
Figure 357. Data Transmission
1118
Table 178. I2C Configuration Table
1119
I2C Slave Mode
1119
Figure 358. Slave Initialization Flowchart
1122
Figure 359. Transfer Sequence Flowchart for I2C Slave Transmitter, NOSTRETCH=0
1123
Figure 360. Transfer Sequence Flowchart for I2C Slave Transmitter, NOSTRETCH=1
1124
Figure 361. Transfer Bus Diagrams for I2C Slave Transmitter
1125
Figure 362. Transfer Sequence Flowchart for Slave Receiver with NOSTRETCH=0
1126
Figure 363. Transfer Sequence Flowchart for Slave Receiver with NOSTRETCH=1
1127
Figure 364. Transfer Bus Diagrams for I2C Slave Receiver
1127
I2C Master Mode
1128
Table 179. I2C-SMBUS Specification Clock Timings
1129
Figure 365. Master Clock Generation
1129
Figure 366. Master Initialization Flowchart
1131
Figure 367. 10-Bit Address Read Access with HEAD10R=0
1131
Figure 368. 10-Bit Address Read Access with HEAD10R=1
1132
Figure 369. Transfer Sequence Flowchart for I2C Master Transmitter for N≤255 Bytes
1133
Figure 370. Transfer Sequence Flowchart for I2C Master Transmitter for N>255 Bytes
1134
Figure 371. Transfer Bus Diagrams for I2C Master Transmitter
1135
Figure 372. Transfer Sequence Flowchart for I2C Master Receiver for N≤255 Bytes
1137
Figure 373. Transfer Sequence Flowchart for I2C Master Receiver for N >255 Bytes
1138
Figure 374. Transfer Bus Diagrams for I2C Master Receiver
1139
Table 180. Examples of Timings Settings for Fi2Cclk = 8 Mhz
1140
Table 181. Examples of Timings Settings for Fi2Cclk = 16 Mhz
1140
I2C_TIMINGR Register Configuration Examples
1140
Table 182. Examples of Timings Settings for Fi2Cclk = 48 Mhz
1141
Smbus Specific Features
1141
Table 183. Smbus Timeout Specifications
1143
Figure 375. Timeout Intervals for T
1144
Table 184. SMBUS with PEC Configuration
1145
(Max T TIMEOUT = 25 Ms)
1146
Table 187. Examples of TIMEOUTA Settings for Various I2CCLK Frequencies
1146
(Max T IDLE = 50 Μs)
1147
Smbus Slave Mode
1147
Figure 376. Transfer Sequence Flowchart for Smbus Slave Transmitter N Bytes + PEC
1148
Figure 377. Transfer Bus Diagrams for Smbus Slave Transmitter (SBC=1)
1148
Figure 378. Transfer Sequence Flowchart for Smbus Slave Receiver N Bytes + PEC
1150
Figure 379. Bus Transfer Diagrams for Smbus Slave Receiver (SBC=1)
1151
Figure 380. Bus Transfer Diagrams for Smbus Master Transmitter
1152
Figure 381. Bus Transfer Diagrams for Smbus Master Receiver
1154
Wakeup from Stop Mode on Address Match
1155
DMA Requests
1157
Table 188. Effect of Low-Power Modes on the I2C
1158
Debug Mode
1158
Table 189. I2C Interrupt Requests
1159
Figure 382. I2C Interrupt Mapping Diagram
1160
Table 173. Interrupt Control Bits
1081
I2C Registers
1160
Control Register 2 (I2C_CR2)
1164
Own Address 1 Register (I2C_OAR1)
1167
Own Address 2 Register (I2C_OAR2)
1168
Timing Register (I2C_TIMINGR)
1169
Timeout Register (I2C_TIMEOUTR)
1170
Interrupt and Status Register (I2C_ISR)
1171
Interrupt Clear Register (I2C_ICR)
1173
PEC Register (I2C_PECR)
1174
Receive Data Register (I2C_RXDR)
1175
Table 190. I2C Register Map and Reset Values
1176
Transmitter (USART)
1178
USART Extended Features
1179
Table 191. Stm32L4X6 USART/UART/LPUART Features
1180
USART Implementation
1180
Figure 383. USART Block Diagram
1182
USART Character Description
1183
Figure 384. Word Length Programming
1184
USART Transmitter
1185
Figure 385. Configurable Stop Bits
1186
Figure 386. TC/TXE Behavior When Transmitting
1187
USART Receiver
1187
Figure 387. Start Bit Detection When Oversampling by 16 or 8
1188
Figure 388. Data Sampling When Oversampling by 16
1192
Figure 389. Data Sampling When Oversampling by 8
1192
Table 192. Noise Detection from Sampled Data
1192
USART Baud Rate Generation
1194
Oversampling by 16 or by 8
1195
Table 194. Tolerance of the USART Receiver When BRR [3:0] = 0000
1196
Tolerance of the USART Receiver to Clock Deviation
1196
Table 195. Tolerance of the USART Receiver When BRR [3:0] Is Different from 0000
1197
USART Auto Baud Rate Detection
1197
Multiprocessor Communication Using USART
1198
Figure 390. Mute Mode Using Idle Line Detection
1199
Figure 391. Mute Mode Using Address Mark Detection
1200
Modbus Communication Using USART
1200
Table 196. Frame Formats
1201
USART Parity Control
1201
USART LIN (Local Interconnection Network) Mode
1202
Figure 392. Break Detection in LIN Mode (11-Bit Break Length - LBDL Bit Is Set)
1203
Figure 393. Break Detection in LIN Mode Vs. Framing Error Detection
1204
USART Synchronous Mode
1204
Figure 394. USART Example of Synchronous Transmission
1205
Figure 395. USART Data Clock Timing Diagram (M Bits = 00)
1205
Figure 396. USART Data Clock Timing Diagram (M Bits = 01)
1206
Figure 397. RX Data Setup/Hold Time
1206
USART Single-Wire Half-Duplex Communication
1207
Figure 398. ISO 7816-3 Asynchronous Protocol
1208
Figure 399. Parity Error Detection Using the 1.5 Stop Bits
1209
USART Irda SIR ENDEC Block
1212
Figure 400. Irda SIR ENDEC- Block Diagram
1213
Figure 401. Irda Data Modulation (3/16) -Normal Mode
1213
USART Continuous Communication in DMA Mode
1214
Figure 402. Transmission Using DMA
1215
Figure 403. Reception Using DMA
1216
Figure 404. Hardware Flow Control between 2 Usarts
1216
Using USART
1216
Figure 405. RS232 RTS Flow Control
1217
Figure 406. RS232 CTS Flow Control
1218
Wakeup from Stop Mode Using USART
1218
Table 197. Effect of Low-Power Modes on the USART
1220
Table 198. USART Interrupt Requests
1220
Figure 407. USART Interrupt Mapping Diagram
1221
USART Registers
1222
Control Register 2 (Usartx_Cr2)
1225
Control Register 3 (Usartx_Cr3)
1229
Baud Rate Register (Usartx_Brr)
1233
Receiver Timeout Register (Usartx_Rtor)
1234
Request Register (Usartx_Rqr)
1235
Interrupt and Status Register (Usartx_Isr)
1236
Interrupt Flag Clear Register (Usartx_Icr)
1241
Receive Data Register (Usartx_Rdr)
1242
Table 199. USART Register Map and Reset Values
1243
Transmitter (LPUART)
1245
LPUART Main Features
1246
LPUART Functional Description
1247
Figure 408. LPUART Block Diagram
1248
LPUART Character Description
1248
Figure 409. Word Length Programming
1250
Figure 410. Configurable Stop Bits
1251
LPUART Transmitter
1251
Figure 411. TC/TXE Behavior When Transmitting
1253
LPUART Receiver
1253
LPUART Baud Rate Generation
1256
Multiprocessor Communication Using LPUART
1257
Table 200. Error Calculation for Programmed Baudrates at Fck = 32,768 Khz
1257
Figure 412. Mute Mode Using Idle Line Detection
1258
Figure 413. Mute Mode Using Address Mark Detection
1259
LPUART Parity Control
1259
Table 201. Frame Formats
1259
Single-Wire Half-Duplex Communication Using LPUART
1260
Figure 414. Transmission Using DMA
1261
Figure 415. Reception Using DMA
1262
Figure 416. Hardware Flow Control between 2 Lpuarts
1263
Figure 417. RS232 RTS Flow Control
1263
Using LPUART
1263
Figure 418. RS232 CTS Flow Control
1264
Table 202. Effect of Low-Power Modes on the LPUART
1265
Wakeup from Stop Mode Using LPUART
1265
Table 203. LPUART Interrupt Requests
1266
LPUART Interrupts
1266
Figure 419. LPUART Interrupt Mapping Diagram
1267
LPUART Registers
1268
Control Register 2 (LPUART_CR2)
1271
Control Register 3 (LPUART_CR3)
1273
Baud Rate Register (LPUART_BRR)
1275
Interrupt & Status Register (LPUART_ISR)
1276
Interrupt Flag Clear Register (LPUART_ICR)
1279
Receive Data Register (LPUART_RDR)
1280
Table 204. LPUART Register Map and Reset Values
1282
Introduction
1283
Table 205. Stm32L4X6 SPI Implementation
1284
Figure 420. SPI Block Diagram
1284
SPI Functional Description
1284
Communications between One Master and One Slave
1285
Figure 421. Full-Duplex Single Master/ Single Slave Application
1285
Figure 422. Half-Duplex Single Master/ Single Slave Application
1286
Figure 423. Simplex Single Master/Single Slave Application
1287
Slave in Receive-Only Mode)
1287
Standard Multi-Slave Communication
1287
Figure 424. Master and Three Independent Slaves
1288
Multi-Master Communication
1288
Figure 425. Multi-Master Application
1289
Slave Select (NSS) Pin Management
1289
Communication Formats
1290
Figure 426. Hardware/Software Slave Select Management
1290
Figure 427. Data Clock Timing Diagram
1291
Configuration of SPI
1292
Figure 428. Data Alignment When Data Length Is Not Equal to 8-Bit or 16-Bit
1292
Procedure for Enabling SPI
1293
Figure 429. Packing Data in FIFO for Transmission and Reception
1296
Figure 430. Master Full Duplex Communication
1299
Figure 431. Slave Full Duplex Communication
1300
Figure 432. Master Full Duplex Communication with CRC
1301
Figure 433. Master Full Duplex Communication in Packed Mode
1302
SPI Status Flags
1303
SPI Error Flags
1304
Figure 434. NSSP Pulse Generation in Motorola SPI Master Mode
1305
NSS Pulse Mode
1305
CRC Calculation
1306
Figure 435. TI Mode Transfer
1306
Table 206. SPI Interrupt Requests
1308
SPI Interrupts
1308
SPI Registers
1309
SPI Control Register 2 (Spix_Cr2)
1311
SPI Status Register (Spix_Sr)
1314
SPI Data Register (Spix_Dr)
1315
SPI Rx CRC Register (Spix_Rxcrcr)
1316
Table 207. SPI Register Map and Reset Values
1317
Introduction
1318
SAI Main Features
1319
Figure 436. Functional Block Diagram
1320
SAI Functional Description
1320
Main SAI Modes
1321
SAI Synchronization Mode
1322
Table 208. External Synchronization Selection
1323
Figure 437. Audio Frame
1323
Audio Data Size
1323
Figure 438. FS Role Is Start of Frame + Channel Side Identification (FSDEF = TRIS = 1)
1325
Figure 439. FS Role Is Start of Frame (FSDEF = 0)
1326
Slot Configuration
1326
Figure 440. Slot Size Configuration with FBOFF = 0 in Sai_Xslotr
1327
Figure 441. First Bit Offset
1327
Figure 442. Audio Block Clock Generator Overview
1328
SAI Clock Generator
1328
Table 209. Example of Possible Audio Frequency Sampling Range
1329
Internal Fifos
1330
Figure 443. AC'97 Audio Frame
1332
AC'97 Link Controller
1332
Figure 444. Example of Typical AC'97 Configuration on Devices Featuring at Least
1333
Embedded Sais (Three External AC'97 Decoders)
1333
Figure 445. SPDIF Format
1334
SPDIF Output
1334
Table 210. SOPD Pattern
1335
Table 211. Parity Bit Calculation
1335
Figure 446. Sai_Xdr Register Ordering
1335
Table 212. Audio Sampling Frequency Versus Symbol Rates (SHARK)
1336
Specific Features
1336
Figure 447. Data Companding Hardware in an Audio Block in the SAI
1338
Figure 448. Tristate Strategy on SD Output Line on an Inactive Slot
1340
Figure 449. Tristate on Output Data Line in a Protocol Like I2S
1341
Error Flags
1341
Figure 450. Overrun Detection Error
1342
Figure 451. FIFO Underrun Event
1342
Disabling the SAI
1344
Table 213. SAI Interrupt Sources
1345
SAI Interrupts
1345
SAI Registers
1346
Configuration Register 2 (SAI_ACR2 / SAI_BCR2)
1350
Frame Configuration Register (SAI_AFRCR / SAI_BFRCR)
1352
Slot Register (SAI_ASLOTR / SAI_BSLOTR)
1354
Interrupt Mask Register 2 (SAI_AIM / SAI_BIM)
1356
Status Register (SAI_ASR / SAI_BSR)
1358
Clear Flag Register (SAI_ACLRFR / SAI_BCLRFR)
1360
Table 214. SAI Register Map and Reset Values
1361
Data Register (SAI_ADR / SAI_BDR)
1361
Figure 452. S1 Signal Coding
1363
Figure 453. S2 Signal Coding
1363
Introduction
1363
SWPMI Main Features
1364
Figure 454. SWPMI Block Diagram
1365
SWPMI Functional Description
1365
Figure 455. SWP Bus States
1367
SWPMI_IO (Internal Transceiver) Bypass
1367
Figure 456. SWP Frame Structure
1368
Transmission Procedure
1368
Figure 457. SWPMI no Software Buffer Mode Transmission
1369
Figure 458. SWPMI no Software Buffer Mode Transmission, Consecutive Frames
1370
Figure 459. SWPMI Multi Software Buffer Mode Transmission
1372
Reception Procedure
1372
Figure 460. SWPMI no Software Buffer Mode Reception
1373
Figure 461. SWPMI Single Software Buffer Mode Reception
1375
Error Management
1377
Figure 462. SWPMI Multi Software Buffer Mode Reception
1377
Figure 463. SWPMI Single Buffer Mode Reception with CRC Error
1378
Loopback Mode
1379
Table 215. Effect of Low-Power Modes on SWPMI
1379
Table 216. Interrupt Control Bits
1380
SWPMI Registers
1381
Table 217. Buffer Modes Selection for Transmission/Reception
1382
SWPMI Bitrate Register (SWPMI_BRR)
1383
SWPMI Interrupt and Status Register (SWPMI_ISR)
1384
SWPMI Interrupt Flag Clear Register (SWPMI_ICR)
1386
SWPMI Interrupt Enable Register (SMPMI_IER)
1387
SWPMI Receive Frame Length Register (SWPMI_RFL)
1388
SWPMI Transmit Data Register (SWPMI_TDR)
1389
SWPMI Receive Data Register (SWPMI_RDR)
1390
SWPMI Option Register (SWPMI_OR)
1391
Table 218. Swpmi Register Map and Reset Values
1392
SDMMC Main Features
1393
Figure 464. "No Response" and "No Data" Operations
1394
Figure 465. (Multiple) Block Read Operation
1394
Figure 466. (Multiple) Block Write Operation
1394
Figure 467. Sequential Read Operation
1395
Figure 468. Sequential Write Operation
1395
Figure 469. SDMMC Block Diagram
1395
SDMMC Functional Description
1395
Table 219. SDMMC I/O Definitions
1396
Figure 470. SDMMC Adapter
1397
Figure 471. Control Unit
1398
Figure 472. SDMMC_CK Clock Dephasing (BYPASS = 0)
1399
Figure 473. SDMMC Adapter Command Path
1399
Figure 474. Command Path State Machine (SDMMC)
1400
Figure 475. SDMMC Command Transfer
1401
Table 220. Command Format
1401
Table 221. Short Response Format
1402
Table 222. Long Response Format
1402
Table 223. Command Path Status Flags
1402
Figure 476. Data Path
1403
Figure 477. Data Path State Machine (DPSM)
1404
Table 224. Data Token Format
1405
Table 225. DPSM Flags
1406
Table 226. Transmit FIFO Status Flags
1407
Table 227. Receive FIFO Status Flags
1407
SDMMC APB2 Interface
1408
Card Functional Description
1409
Operating Voltage Range Validation
1410
Block Write
1411
Block Read
1412
Erase: Group Erase and Sector Erase
1414
Table 228. Card Status
1418
Card Status Register
1418
SD Status Register
1420
Table 229. SD Status
1421
Table 230. Speed Class Code Field
1422
Table 231. Performance Move Field
1422
Table 232. AU_SIZE Field
1423
Table 233. Maximum au Size
1423
Table 234. Erase Size Field
1424
Table 235. Erase Timeout Field
1424
Table 236. Erase Offset Field
1424
SD I/O Mode
1425
Commands and Responses
1426
Table 237. Block-Oriented Write Commands
1427
Table 238. Block-Oriented Write Protection Commands
1427
Table 239. Erase Commands
1428
Table 240. I/O Mode Commands
1428
Table 241. Lock Card
1428
Table 242. Application-Specific Commands
1429
Table 243. R1 Response
1429
Response Formats
1429
R2 (CID, CSD Register)
1430
Table 244. R2 Response
1430
R3 (OCR Register)
1431
Table 245. R3 Response
1431
Table 246. R4 Response
1431
Table 247. R4B Response
1431
R5 (Interrupt Request)
1432
Table 248. R5 Response
1432
Table 249. R6 Response
1433
SDIO I/O Card-Specific Operations
1433
SDIO Read Wait Operation by Stopping SDMMC_CK
1434
SDMMC Registers
1435
SDMMC Argument Register (SDMMC_ARG)
1437
SDMMC Command Response Register (SDMMC_RESPCMD)
1438
Table 250. Response Type and Sdmmc_Respx Registers
1439
SDMMC Data Timer Register (SDMMC_DTIMER)
1439
SDMMC Data Length Register (SDMMC_DLEN)
1440
SDMMC Data Counter Register (SDMMC_DCOUNT)
1442
SDMMC Interrupt Clear Register (SDMMC_ICR)
1443
SDMMC Mask Register (SDMMC_MASK)
1445
SDMMC FIFO Counter Register (SDMMC_FIFOCNT)
1447
SDMMC Data FIFO Register (SDMMC_FIFO)
1448
Table 251. SDMMC Register Map
1449
Introduction
1451
Figure 478. CAN Network Topology
1452
Bxcan General Description
1452
Acceptance Filters
1453
Sleep Mode (Low-Power)
1454
Figure 479. Bxcan Operating Modes
1455
Test Mode
1455
Figure 480. Bxcan in Silent Mode
1456
Figure 481. Bxcan in Loop Back Mode
1456
Behavior in Debug Mode
1457
Figure 482. Bxcan in Combined Mode
1457
Figure 483. Transmit Mailbox States
1458
Figure 484. Receive FIFO States
1459
Time Triggered Communication Mode
1459
Identifier Filtering
1460
Figure 485. Filter Bank Scale Configuration - Register Organization
1462
Figure 486. Example of Filter Numbering
1463
Figure 487. Filtering Mechanism - Example
1464
Message Storage
1464
Figure 488. CAN Error State Diagram
1465
Table 252. Transmit Mailbox Mapping
1465
Table 253. Receive Mailbox Mapping
1465
Error Management
1466
Figure 489. Bit Timing
1467
Figure 490. CAN Frames
1468
Figure 491. Event Flags and Interrupt Generation
1469
Bxcan Interrupts
1469
CAN Registers
1470
CAN Mailbox Registers
1480
Figure 492. Can Mailbox Registers
1481
CAN Filter Registers
1487
Table 254. Bxcan Register Map and Reset Values
1491
Introduction
1495
Host-Mode Features
1496
Table 255. USB_OTG Implementation for Stm32L4Xx
1497
Peripheral-Mode Features
1497
Figure 493. OTG Full-Speed Block Diagram
1498
USB OTG Functional Description
1498
Full-Speed OTG PHY
1499
Figure 494. OTG_FS A-B Device Connection
1500
OTG Dual Role Device (DRD)
1500
SRP Dual Role Device
1501
Figure 495. USB_FS Peripheral-Only Connection
1502
SRP-Capable Peripheral
1502
Peripheral Endpoints
1503
USB Host
1505
Figure 496. USB_FS Host-Only Connection
1506
SRP-Capable Host
1506
Host Channels
1508
Host Scheduler
1509
Figure 497. SOF Connectivity (SOF Trigger Output to TIM and ITR1 Connection)
1510
Power Options
1511
Dynamic Update of the OTG_HFIR Register
1512
Figure 498. Updating OTG_HFIR Dynamically
1512
Figure 499. Device-Mode FIFO Address Mapping and AHB FIFO Access Mapping
1513
Peripheral FIFO Architecture
1513
Figure 500. Host-Mode FIFO Address Mapping and AHB FIFO Access Mapping
1514
Host FIFO Architecture
1514
FIFO RAM Allocation
1515
OTG_FS System Performance
1516
Figure 501. Interrupt Hierarchy
1517
OTG_FS Interrupts
1517
Table 256. Core Global Control and Status Registers (Csrs)
1518
Table 257. Host-Mode Control and Status Registers (Csrs)
1519
Table 258. Device-Mode Control and Status Registers
1520
OTG_FS Registers
1522
OTG Interrupt Register (OTG_GOTGINT)
1524
OTG AHB Configuration Register (OTG_GAHBCFG)
1526
Table 261. TRDT Values
1528
OTG Reset Register (OTG_GRSTCTL)
1528
OTG Core Interrupt Register (OTG_GINTSTS)
1530
OTG Interrupt Mask Register (OTG_GINTMSK)
1534
OTG_FS Receive Status Debug Read/Otg Status Read and Pop Registers (OTG_GRXSTSR/OTG_GRXSTSP)
1537
OTG Receive FIFO Size Register (OTG_GRXFSIZ)
1539
OTG General Core Configuration Register (OTG_GCCFG)
1542
OTG Core ID Register (OTG_CID)
1543
OTG Core LPM Configuration Register (OTG_GLPMCFG)
1544
OTG Power down Register (OTG_GPWRDN)
1548
Host-Mode Registers
1551
OTG Host Frame Interval Register (OTG_HFIR)
1552
OTG Host All Channels Interrupt Register (OTG_HAINT)
1555
OTG Host Port Control and Status Register (OTG_HPRT)
1556
Device-Mode Registers
1563
OTG Device Control Register (OTG_DCTL)
1564
Table 262. Minimum Duration for Soft Disconnect
1565
OTG Device Status Register (OTG_DSTS)
1566
OTG Device All Endpoints Interrupt Register (OTG_DAINT)
1568
OTG Power and Clock Gating Control Register (OTG_PCGCCTL)
1585
Table 263. OTG_FS Register Map and Reset Values
1586
Core Initialization
1594
Host Initialization
1595
Host Programming Model
1596
Figure 502. Transmit FIFO Write Task
1597
Figure 503. Receive FIFO Read Task
1598
Figure 504. Normal Bulk/Control OUT/SETUP
1599
Figure 505. Bulk/Control in Transactions
1603
Figure 506. Normal Interrupt out
1606
Figure 507. Normal Interrupt in
1610
Figure 508. Isochronous out Transactions
1612
Figure 509. Isochronous in Transactions
1615
Device Programming Model
1616
Figure 510. Receive FIFO Packet Read
1620
Figure 511. Processing a SETUP Packet
1622
Figure 512. Bulk out Transaction
1628
Worst Case Response Time
1636
Figure 513. TRDT Max Timing Case
1638
OTG Programming Model
1638
Figure 514. A-Device SRP
1639
Figure 515. B-Device SRP
1640
Figure 516. A-Device HNP
1641
Figure 517. B-Device HNP
1643
Figure 518. Block Diagram of STM32 MCU and Cortex ® -M4-Level Debug Support
1645
Reference ARM® Documentation
1646
Figure 519. SWJ Debug Port
1647
Mechanism to Select the JTAG-DP or the SW-DP
1647
Table 264. SWJ Debug Port Pins
1648
Table 265. Flexible SWJ-DP Pin Assignment
1648
Internal Pull-Up and Pull-Down on JTAG Pins
1649
Using Serial Wire and Releasing the Unused Debug Pins as Gpios
1650
Figure 520. JTAG TAP Connections
1651
Table 259. Data FIFO (DFIFO) Access Register Map
1522
Table 260. Power and Clock Gating Control and Status Registers
1522
ID Codes and Locking Mechanism
1651
MCU Device ID Code
1652
Table 266. JTAG Debug Port Data Registers
1653
Table 267. 32-Bit Debug Port Registers Addressed through the Shifted Value A[3:2]
1654
Table 268. Packet Request (8-Bits)
1655
SW Debug Port
1655
SW-DP State Machine (Reset, Idle States, ID Code)
1656
Table 269. ACK Response (3 Bits)
1656
Table 270. DATA Transfer (33 Bits)
1656
Table 271. SW-DP Registers
1657
SW-AP Registers
1658
Table 272. Cortex ® -M4 AHB-AP Registers
1658
Table 273. Core Debug Registers
1659
FPB (Flash Patch Breakpoint)
1660
ITM (Instrumentation Trace Macrocell)
1661
Table 274. Main ITM Registers
1661
ETM (Embedded Trace Macrocell)
1663
Configuration Example
1664
Debug MCU Configuration Register (DBGMCU_CR)
1665
Debug MCU APB1 Freeze Register1(DBGMCU_APB1FZR1)
1667
Debug MCU APB1 Freeze Register 2 (DBGMCU_APB1FZR2)
1669
Debug MCU APB2 Freeze Register (DBGMCU_APB2FZR)
1670
Table 276. Asynchronous TRACE Pin Assignment
1671
Figure 521. TPIU Block Diagram
1671
Table 275. Main ETM Registers
1663
TPIU (Trace Port Interface Unit)
1671
Table 277. Synchronous TRACE Pin Assignment
1672
Table 278. Flexible TRACE Pin Assignment
1672
TPUI Formatter
1673
TPUI Frame Synchronization Packets
1674
Asynchronous Mode
1675
Table 279. Important TPIU Registers
1676
Example of Configuration
1677
Table 280. DBG Register Map and Reset Values
1678
Device Electronic Signature
1679
Flash Size Data Register
1680
Package Data Register
1681
Table 281. Document Revision History
1688
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ST STM32L4x6 Specifications
General
Brand
ST
Model
STM32L4x6
Category
Microcontrollers
Language
English
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