Address: 4003_7000h base + 0h offset = 4003_7000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
Reserved
MDIS FRZ
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
PIT_MCR field descriptions
Field Description
31–3
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
2
Reserved
This field is reserved.
1
MDIS
Module Disable - (PIT section)
Disables the standard timers. This field must be enabled before any other setup is done.
0 Clock for standard PIT timers is enabled.
1 Clock for standard PIT timers is disabled.
0
FRZ
Freeze
Allows the timers to be stopped when the device enters the Debug mode.
0 Timers continue to run in Debug mode.
1 Timers are stopped in Debug mode.
Memory map/register description
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
1032 NXP Semiconductors
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