SPIx_MCR field descriptions (continued)
Field Description
0 Continuous SCK disabled.
1 Continuous SCK enabled.
29–28
DCONF
SPI Configuration.
Selects among the different configurations of the module.
00 SPI
01 Reserved
10 Reserved
11 Reserved
27
FRZ
Freeze
Enables transfers to be stopped on the next frame boundary when the device enters Debug mode.
0 Do not halt serial transfers in Debug mode.
1 Halt serial transfers in Debug mode.
26
MTFE
Modified Transfer Format Enable
Enables a modified transfer format to be used.
0 Modified SPI transfer format disabled.
1 Modified SPI transfer format enabled.
25
PCSSE
Peripheral Chip Select Strobe Enable
Enables the PCS5/ PCSS to operate as a PCS Strobe output signal.
0 PCS5/ PCSS is used as the Peripheral Chip Select[5] signal.
1 PCS5/ PCSS is used as an active-low PCS Strobe signal.
24
ROOE
Receive FIFO Overflow Overwrite Enable
In the RX FIFO overflow condition, configures the module to ignore the incoming serial data or overwrite
existing data. If the RX FIFO is full and new data is received, the data from the transfer, generating the
overflow, is ignored or shifted into the shift register.
0 Incoming data is ignored.
1 Incoming data is shifted into the shift register.
23–22
Reserved
Always write the reset value to this field.
This field is reserved.
21–16
PCSIS
Peripheral Chip Select x Inactive State
Determines the inactive state of PCSx. Refer to the chip-specific SPI information for the number of PCS
signals used in this chip.
NOTE:
The effect of this bit only takes place when module is enabled. Ensure that this bit is configured
correctly before enabling the SPI interface.
0 The inactive state of PCSx is low.
1 The inactive state of PCSx is high.
15
DOZE
Doze Enable
Provides support for an externally controlled Doze mode power-saving mechanism.
Table continues on the next page...
Chapter 45 Serial Peripheral Interface (SPI)
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 1133
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