45.4.3.5 Peripheral Chip Select Strobe Enable (PCSS )
The PCSS signal provides a delay to allow the PCS signals to settle after a transition
occurs thereby avoiding glitches. When the Module is in Master mode and the PCSSE bit
is set in the MCR, PCSS provides a signal for an external demultiplexer to decode
peripheral chip selects other than PCS5 into glitch-free PCS signals. The following figure
shows the timing of the PCSS signal relative to PCS signals.
Figure 45-5. Peripheral Chip Select Strobe timing
The delay between the assertion of the PCS signals and the assertion of PCSS is selected
by the PCSSCK field in the CTAR based on the following formula:
At the end of the transfer, the delay between PCSS negation and PCS negation is selected
by the PASC field in the CTAR based on the following formula:
The following table shows an example of how to compute the t
pcssck
delay.
Table 45-9. Peripheral Chip Select Strobe Assert computation example
f
P
PCSSCK Prescaler Delay before Transfer
100 MHz 0b11 7 70.0 ns
The following table shows an example of how to compute the t
pasc
delay.
Table 45-10. Peripheral Chip Select Strobe Negate computation example
f
P
PASC Prescaler Delay after Transfer
100 MHz 0b11 7 70.0 ns
The PCSS signal is not supported when Continuous Serial Communication SCK mode is
enabled.
Chapter 45 Serial Peripheral Interface (SPI)
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 1159
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