USB controller
FS/LS
transceiver
USB voltage
regulator
D+ D-
VREGIN
VOUT33
IRC 48
Figure 3-46. USB FS/LS Subsystem Overview
NOTE
Use the following code sequence to select USB clock source,
USB clock divide ratio, and enable its clock gate to avoid
potential clock glitches which may result in USB enumeration
stage failure.
1. Select the USB clock source by configuring SIM_SOPT2.
2. Select the desired clock divide ratio by configuring
SIM_CLKDIV2.
3. Enable USB clock gate by setting SIM_SCGC4.
3.9.1.1
USB pin status detection and wakeup interrupt features
This device does not have a dedicated VBUS detect pin. For VBUS detection, use a
GPIO pin for both bus-powered and self-powered USB cases. Because the GPIO pins on
this device do not directly support a 5V input, use an external resistive voltage divider to
keep the input voltage within the valid range if a GPIO pin is used for VBUS detection.
This device does not have a dedicated OTG ID detect pin. For OTG ID pin detection, if
needed, use a GPIO configured as an input pin with pullup enabled.
When the USB detects that there is no activity on the USB bus for more than 3 ms, the
USBx_ISTAT[SLEEP] bit is set. This bit can cause an interrupt and software decides the
appropriate action.
Waking from a low power mode (except in LLS/VLLS mode where USB is not powered)
occurs through an asynchronous interrupt triggered by activity on the USB bus. Setting
the USBx_USBTRC0[USBRESMEN] bit enables this function.
The following wakeup feature is also supported:
• In LLS/VLLS, if the GPIO pins chosen to detect VBUS and OTG ID are selected
from those pins which are inputs to the LLWU, transitions on them can generate a
wakeup.
Communication interfaces
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
122 NXP Semiconductors
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