Table 3-62. Reference links to related information (continued)
Topic Related module Reference
System memory map System memory map
Clocking Clock Distribution
Signal Multiplexing Port control Signal Multiplexing
3.9.2.1 SPI Modules Configuration
This device contains two SPI modules .
3.9.2.2 SPI clocking
The SPI module is clocked by the internal bus clock (the DSPI refers to it as system
clock). The module has an internal divider, with a minimum divide is two. So, the SPI
can run at a maximum frequency of bus clock/2.
3.9.2.3
Number of CTARs
SPI CTAR registers define different transfer attribute configurations. The SPI module
supports up to eight CTAR registers. This device supports two CTARs on all instances of
the SPI.
In master mode, the CTAR registers define combinations of transfer attributes, such as
frame size, clock phase, clock polarity, data bit ordering, baud rate, and various delays. In
slave mode only CTAR0 is used, and a subset of its bitfields sets the slave transfer
attributes.
3.9.2.4
TX FIFO size
Table 3-63. SPI transmit FIFO size
SPI Module Transmit FIFO size
SPI0 4
SPI1 1
Chapter 3 Chip Configuration
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 127
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