NXP Semiconductors K22F series - Page 128

3.9.2.5 RX FIFO Size
SPI supports up to 16-bit frame size during reception.
Table 3-64. SPI receive FIFO size
SPI Module Receive FIFO size
SPI0 4
SPI1 1
3.9.2.6 Number of PCS signals
The following table shows the number of peripheral chip select signals available per SPI
module.
Table 3-65. SPI PCS signals
SPI Module PCS Signals
SPI0 For packages with greater than 64 pins: SPI_PCS[5:0]
For packages with 64 pins: SPI_PCS[4:0]
SPI1 For packages with greater than 64 pins: SPI_PCS[3:0]
For packages with 64 pins: SPI_PCS[1:0]
3.9.2.7 SPI Operation in Low Power Modes
In VLPR and VLPW modes the SPI is functional; however, the reduced system
frequency also reduces the max frequency of operation for the SPI. In VLPR and VLPW
modes the max SPI_CLK frequency is 2MHz.
In stop and VLPS modes, the clocks to the SPI module are disabled. The module is not
functional, but it is powered so that it retains state.
There is one way to wake from stop mode via the SPI, which is explained in the
following section.
3.9.2.7.1
Using GPIO Interrupt to Wake from stop mode
Here are the steps to use a GPIO to create a wakeup upon reception of SPI data in slave
mode:
1. Point the GPIO interrupt vector to the desired interrupt handler.
Communication interfaces
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
128 NXP Semiconductors