NXP Semiconductors K22F series - Page 129

2. Enable the GPIO input to generate an interrupt on either the rising or falling edge
(depending on the polarity of the chip select signal).
3. Enter Stop or VLPS mode and Wait for the GPIO interrupt.
NOTE
It is likely that in using this approach the first word of data from
the SPI host might not be received correctly. This is dependent
on the transfer rate used for the SPI, the delay between chip
select assertion and presentation of data, and the system
interrupt latency.
3.9.2.8 SPI Doze Mode
The Doze mode for the SPI module is the same as the Wait and VLPW modes for the
chip.
3.9.2.9 SPI Interrupts
The SPI has multiple sources of interrupt requests. However, these sources are OR'd
together to generate a single interrupt request per SPI module to the interrupt controller.
When an SPI interrupt occurs, read the SPI_SR to determine the exact interrupt source.
3.9.2.10
SPI clocks
This table shows the SPI module clocks and the corresponding chip clocks.
Table 3-66. SPI clock connections
Module clock Chip clock
System Clock Bus Clock
3.9.2.11 Writing SPI Transmit FIFO
The SPI supports 8-bit or 16-bit writes to the PUSH TX FIFO, allowing a single write to
the command word followed by multiple writes to the transmit word. The TX FIFO will
save the last command word written, and convert a 8-bit/16-bit write to the transmit word
into a 32-bit write that pushes both the command word and transmit word into the TX
FIFO (PUSH TX FIFO Register In Master Mode)
Chapter 3 Chip Configuration
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 129