NXP Semiconductors K22F series - Page 13

Section number Title Page
16.3 Low-voltage detect (LVD) system................................................................................................................................371
16.3.1 LVD reset operation.....................................................................................................................................372
16.3.2 LVD interrupt operation...............................................................................................................................372
16.3.3 Low-voltage warning (LVW) interrupt operation....................................................................................... 372
16.4 I/O retention..................................................................................................................................................................373
16.5 Memory map and register descriptions.........................................................................................................................373
16.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1)........................................................ 374
16.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2)........................................................ 375
16.5.3 Regulator Status And Control register (PMC_REGSC)..............................................................................376
Chapter 17
Low-Leakage Wakeup Unit (LLWU)
17.1 Introduction...................................................................................................................................................................379
17.1.1 Features........................................................................................................................................................ 379
17.1.2 Modes of operation...................................................................................................................................... 380
17.1.3 Block diagram..............................................................................................................................................381
17.2 LLWU signal descriptions............................................................................................................................................ 382
17.3 Memory map/register definition................................................................................................................................... 382
17.3.1 LLWU Pin Enable 1 register (LLWU_PE1)................................................................................................383
17.3.2 LLWU Pin Enable 2 register (LLWU_PE2)................................................................................................384
17.3.3 LLWU Pin Enable 3 register (LLWU_PE3)................................................................................................385
17.3.4 LLWU Pin Enable 4 register (LLWU_PE4)................................................................................................386
17.3.5 LLWU Module Enable register (LLWU_ME)............................................................................................ 387
17.3.6 LLWU Flag 1 register (LLWU_F1).............................................................................................................389
17.3.7 LLWU Flag 2 register (LLWU_F2).............................................................................................................391
17.3.8 LLWU Flag 3 register (LLWU_F3).............................................................................................................392
17.3.9 LLWU Pin Filter 1 register (LLWU_FILT1).............................................................................................. 394
17.3.10 LLWU Pin Filter 2 register (LLWU_FILT2).............................................................................................. 395
17.4 Functional description...................................................................................................................................................396
17.4.1 LLS mode.....................................................................................................................................................397
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 13