A.35 CMP changes
• Updated the field description of CFF and CFR in CMP Status and Control Register to show CMP interrupts are edge
sensitive only
A.36 DAC changes
• No substantial content changes
A.37 VREF changes
• Added Internal Voltage Regulator topic to the chapter.
A.38 PDB changes
• In PDB trigger input source selection section, the sentence "SC[TRIGSEL] selects the active trigger input source or
software trigger." was removed.
• In "Pulse-Out's" section, added a Pulse-Out generation diagram.
• Updated LDOK with a slightly more clear description.
• Added a note about SC[LDOK] to Modulus register (PDB_MOD), Interrupt Delay register (PDB_IDLY), PODLY,
DACINTx, and registers.
• Deleted “PDB signal description” section.
• In Pulse-Out n Enable register (POEN), in bit POEN (PDB Pulse-Out Enable), changed "Enables the pulse output.
Only lower Y bits are implemented in this MCU." to "Enables the pulse output. Only lower 8 bits are implemented in
this MCU."
A.39 FTM changes
• Added the following note to Introduction, Block diagram, and Memory map sections:
"The number of channels supported can vary for each instance of the FTM module on a chip. See the chip-specific
FTM information to see how many channels are supported for each module instance. For example, if a module
instance supports only six channels, references to channel numbers 6 and 7 do not apply for that instance."
• Updated feature list to add "Initialization trigger"
• For section "Counter clock source", changed "SC register selects clock sources" to "SC register selects one of three
possible clock sources"
• Made the following changes to section Channel trigger output to clarify external trigger functionality:
Appendix A Release Notes for Revision 4
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 1403
To Next Page
Loading...
