NXP Semiconductors K22F series - Page 1404

• Updated figure "Channel match trigger"
• Updated the first two paragraphs to "If CH(j)TRIG bit of the FTM External Trigger (FTM_EXTTRIG) register is
set, where j = 0, 1, 2, 3, 4, or 5, then the FTM generates a trigger when the channel (j) match occurs (FTM
counter = C(j)V). The channel trigger output provides a trigger signal which has one FTM clock period width and
is used for on-chip modules."
• In FTM_EXTTRIG register description, added cross-references to Channel trigger output and Initialization trigger
sections
• Updated description of FTM_SC[CLKS] field
• In section Edge-Aligned PWM (EPWM) mode, updated sentence to read as follows: "If (CnV > MOD), then the channel
(n) output is a 100% duty cycle EPWM signal and CHnF bit is not set even when there is the channel (n) match."
• For section "Modes of operation" and section "Counter clock source", changed "MCU" to "chip"
• For section "Counter clock source", changed "Refer to the chip specific documentation for further information." to "see
the chip-specific FTM information for further details."
• Added more details about input capture delay on section "Filter for Input Capture mode".
• Corrected "Channel input filter example" figure on section "Filter for Input Capture mode".
A.40 PIT module changes
• No substantial content changes
A.41 LPTMR changes
Added a note to the LPTMR_CNR register.
A.42 RTC changes
• No substantial content changes
A.43 USB full speed OTG controller changes
Added new topic under "Functional description": "On-chip transceiver required external components."
A.44 USB VREG changes
• No substantial content changes
PIT module changes
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
1404 NXP Semiconductors