A.45 SPI module changes
• Included two topics Modified SPI Transfer Format (MTFE = 1, CPHA = 0) and Modified SPI Transfer Format (MTFE =
1, CPHA = 1).
• Reduced bit width of SPI_CTARn_SLAVE [FMSZ] from 5 to 4 and updating the bit to reserved.
• In RSER register, added "Always write the reset value to this field." to some of the Reserved bits. Also, updated bit
field access to RW for these bits.
• In PUSHR register, added note "Always write the reset value to this field." to Reserved bits. Also, updated bit field
access to RW for these bits.
• In MCR register, updated bit field access to RW for Reserved bit fields 22 and 23. Also updated bit field description
with text, "Always write the reset value to this field".
• In Memory Map/Register Definition section, added RXFRn to statement re. write accesses results in transfer error.
• Updated bit field description for SPI_MCR[PCSIS].
• Updated bit field description for SPI_PUSHR[PCS].
• Updated section, Continuous Serial Communications Clock
• Editorial updates.
• In "SPI memory map" table of Memory Map/Register Definition section, changed reset value of Status Register from
"See section" to actual value.
• Updated bit field description for SPI_MCR[MTFE]
• In Section, Classic SPI Transfer Format (CPHA = 0), changed "After the tASC delay elapses, the master outputs the
first edge of SCK"to "After the tCSC delay elapses..."
• Updated SPI_MCR[MDIS] bit field description for setting default reset value to 1 instead of 0.
• In SPI_CTARn[FMSZ], updated description of 'fr' to 'register interface clock frequency'.
• Updated SPI_PUSHR register description.
• Updated SPI_PUSHR_SLAVE register description.
• Updated bit field description and width for SPI_PUSHR_SLAVE[TXDATA]
• Added note to SPI_MCR[PCSIS] bit field.
• Updated bit field description for SPI_TXFRn[TXCMD_TXDATA].
• Changed "MCU" to "chip" throughout the chapter.
• Removed note from Section, SIN—Serial Input
• Added note to SPI_SR[TFFF] bit field.
• In Section, Modified SPI Transfer Format (MTFE = 1, CPHA = 1), added note, "When using MTFE=1...POP operation."
• In Modified SPI Transfer Format (MTFE = 1, CPHA = 1) - Updated note.
• Previous Errata moved to documentation: In Module Configuration Register (SPI_MCR), note to the
SPI_MCR[CLR_RXF] bit field description.
• In Status Register (SPI_SR) - Changed TXRXS bitfield access from W1C to RO.
• In PCS0/SS—Peripheral Chip Select/Slave Select - Added note.
• Deleted note from SOUT—Serial Output.
• Clarified Memory Map/Register Definition introductory text by changing second sentence:
• From: "Write access to the POPR and RXFRn also results in a transfer error."
• To: "Any Write access to the POPR and RXFRn also results in a transfer error."
• In section, PCS0/SS—Peripheral Chip Select/Slave Select : Updated note.
Appendix A Release Notes for Revision 4
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 1405
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