NXP Semiconductors K22F series - Page 17

Section number Title Page
22.3.32 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_CITER_ELINKNO)............................................................................................................ 477
22.3.33
TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCDn_DLASTSGA).......... 478
22.3.34
TCD Control and Status (DMA_TCDn_CSR)............................................................................................ 479
22.3.35 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_BITER_ELINKYES)...........................................................................................................481
22.3.36 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_BITER_ELINKNO)............................................................................................................ 482
22.4 Functional description...................................................................................................................................................483
22.4.1 eDMA basic data flow................................................................................................................................. 483
22.4.2 Fault reporting and handling........................................................................................................................486
22.4.3 Channel preemption..................................................................................................................................... 489
22.4.4 Performance................................................................................................................................................. 489
22.5 Initialization/application information........................................................................................................................... 493
22.5.1 eDMA initialization..................................................................................................................................... 493
22.5.2 Programming errors..................................................................................................................................... 495
22.5.3 Arbitration mode considerations..................................................................................................................496
22.5.4 Performing DMA transfers.......................................................................................................................... 496
22.5.5 Monitoring transfer descriptor status........................................................................................................... 500
22.5.6 Channel Linking...........................................................................................................................................502
22.5.7 Dynamic programming................................................................................................................................ 503
22.5.8 Lockstep.......................................................................................................................................................507
Chapter 23
External Watchdog Monitor (EWM)
23.1 Introduction...................................................................................................................................................................509
23.1.1 Features........................................................................................................................................................ 509
23.1.2 Modes of Operation..................................................................................................................................... 510
23.1.3 Block Diagram............................................................................................................................................. 511
23.2 EWM Signal Descriptions............................................................................................................................................ 512
23.3 Memory Map/Register Definition.................................................................................................................................512
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 17