NXP Semiconductors K22F series - Page 192

Table 7-2. Module operation in low power modes (continued)
Modules VLPR VLPW Stop VLPS LLSx VLLSx
4 MHz max in
PSTOP2 from
VLPR
Memory and memory interfaces
Flash 1 MHz max
access - no
program/erase
No register
access in CPO
low power low power low power OFF OFF
System RAM
(SRAM_U and
SRAM_L)
4
low power low power low power low power low power in
LLS3, partial in
LLS2
low power in
VLLS3, partial in
VLLS2;
otherwise OFF
VBAT Register
file
5
powered powered powered powered powered powered
System Register
files
powered powered powered powered powered powered
FlexBus FF, disabled in
CPO
FF static static static OFF
EzPort disabled disabled disabled disabled disabled disabled
Communication interfaces
USB FS/LS static, wakeup
on resume
static, wakeup
on resume
static, wakeup
on resume
static, wakeup
on resume
static OFF
USB Voltage
Regulator
optional optional optional optional optional optional
UART0, UART1 250 kbit/s
static, wakeup
on edge in CPO
250 kbit/s static, wakeup
on edge
static, wakeup
on edge
static OFF
UART2 250kbit/s
static, wakeup
on edge in CPO
250 kbit/s static, wakeup
on edge
FF in PSTOP2
static, wakeup
on edge
static OFF
LPUART0 4 Mbps
Async operation
in CPO
4 Mbps Async operation
FF in PSTOP2
Async operation static OFF
SPI 1 Mbit/s (slave)
2 Mbit/s
(master)
static in CPO
1 Mbit/s (slave)
2 Mbit/s
(master)
static
FF in PSTOP2
static static OFF
I
2
C 200 kbit/s
static, address
match wakeup
in CPO
200 kbit/s static, address
match wakeup
FF in PSTOP2
static, address
match wakeup
static OFF
I
2
S FF
Async operation
in CPO
FF Async operation
with external
clock
6
FF with external
clock
6
static OFF
Table continues on the next page...
Module Operation in Low Power Modes
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
192 NXP Semiconductors