NXP Semiconductors K22F series - Page 193

Table 7-2. Module operation in low power modes (continued)
Modules VLPR VLPW Stop VLPS LLSx VLLSx
FF in PSTOP2
Security
CRC FF
static in CPO
FF static static static OFF
RNG FF
static in CPO
FF
static in CPO
static static static OFF
Timers
FTM FF
static in CPO
FF static
FF in PSTOP2
static static OFF
PIT FF
static in CPO
FF static
FF in PSTOP2
static static OFF
PDB FF
static in CPO
FF static
FF in PSTOP2
static static OFF
LPTMR FF FF Async operation
FF in PSTOP2
Async operation Async operation Async
operation
7
RTC - 32kHz
OSC
5
FF
Async operation
in CPO
FF Async operation
FF in PSTOP2
Async operation Async
operation
8
Async
operation
8
Analog
16-bit ADC FF
ADACK and
ALTCLK clocks
only in CPO
FF ADACK,
ALTCLK, and
ALTCLK2 clocks
only
FF in PSTOP2
ADACK and
ALTCLK clocks
only
static OFF
CMP
9
FF
HS or LS
compare in CPO
FF HS or LS
compare
FF in PSTOP2
HS or LS
compare
LS compare LS compare in
VLLS1/2/3, OFF
in VLLS0
6-bit DAC FF
static in CPO
FF static
FF in PSTOP2
static static static, OFF in
VLLS0
VREF FF FF FF FF static OFF
12-bit DAC FF
static in CPO
FF static
FF in PSTOP2
static static static
Human-machine interfaces
GPIO FF
GPIO write only
in CPO
FF static output,
wakeup input
FF in PSTOP2
static output,
wakeup input
static, pins
latched
OFF, pins
latched
1. Using the LLWU module, the external pins available for this chip do not require the associated peripheral function to be
enabled. It only requires the function controlling the pin (GPIO or peripheral) to be configured as an input to allow a
transition to occur to the LLWU.
2. Since LPO clock source is disabled, filters will be bypassed during VLLS0
3. The SMC_STOPCTRL[PORPO] bit in the SMC module controls this option.
Chapter 7 Power Management
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 193