64
MAP
BGA
64
LQFP
80
WLC
SP
88
QFN
100
LQFP
121
MAP
BGA
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EZPORT
C6 44 B1 61 71 D8 PTC1/
LLWU_P6
ADC0_
SE15
ADC0_
SE15
PTC1/
LLWU_P6
SPI0_
PCS3
UART1_
RTS_b
FTM0_
CH0
FB_AD13 I2S0_
TXD0
LPUART0
_RTS_b
B7 45 C2 62 72 C8 PTC2 ADC0_
SE4b/
CMP1_IN0
ADC0_
SE4b/
CMP1_IN0
PTC2 SPI0_
PCS2
UART1_
CTS_b
FTM0_
CH1
FB_AD12 I2S0_TX_
FS
LPUART0
_CTS_b
C8 46 C3 63 73 B8 PTC3/
LLWU_P7
CMP1_IN1 CMP1_IN1 PTC3/
LLWU_P7
SPI0_
PCS1
UART1_
RX
FTM0_
CH2
CLKOUT I2S0_TX_
BCLK
LPUART0
_RX
E3 47 E5 64 74 — VSS VSS VSS
E4 48 D6 65 75 — VDD VDD VDD
B8 49 A1 66 76 A8 PTC4/
LLWU_P8
DISABLE
D
PTC4/
LLWU_P8
SPI0_
PCS0
UART1_
TX
FTM0_
CH3
FB_AD11 CMP1_
OUT
LPUART0
_TX
A8 50 B2 67 77 D7 PTC5/
LLWU_P9
DISABLE
D
PTC5/
LLWU_P9
SPI0_SCK LPTMR0_
ALT2
I2S0_
RXD0
FB_AD10 CMP0_
OUT
FTM0_
CH2
A7 51 A2 68 78 C7 PTC6/
LLWU_
P10
CMP0_IN0 CMP0_IN0 PTC6/
LLWU_
P10
SPI0_
SOUT
PDB0_
EXTRG
I2S0_RX_
BCLK
FB_AD9 I2S0_
MCLK
B6 52 B3 69 79 B7 PTC7 CMP0_IN1 CMP0_IN1 PTC7 SPI0_SIN USB_
SOF_OUT
I2S0_RX_
FS
FB_AD8
A6 53 A3 70 80 A7 PTC8 ADC1_
SE4b/
CMP0_IN2
ADC1_
SE4b/
CMP0_IN2
PTC8 FTM3_
CH4
I2S0_
MCLK
FB_AD7
B5 54 C4 — 81 D6 PTC9 ADC1_
SE5b/
CMP0_IN3
ADC1_
SE5b/
CMP0_IN3
PTC9 FTM3_
CH5
I2S0_RX_
BCLK
FB_AD6 FTM2_
FLT0
B4 55 B4 — 82 C6 PTC10 ADC1_
SE6b
ADC1_
SE6b
PTC10 I2C1_SCL FTM3_
CH6
I2S0_RX_
FS
FB_AD5
A5 56 A4 — 83 C5 PTC11/
LLWU_
P11
ADC1_
SE7b
ADC1_
SE7b
PTC11/
LLWU_
P11
I2C1_SDA FTM3_
CH7
FB_RW_b
— — — 71 84 B6 PTC12 DISABLE
D
PTC12 FB_AD27 FTM3_
FLT0
— — — 72 85 A6 PTC13 DISABLE
D
PTC13 FB_AD26
— — — 73 86 A5 PTC14 DISABLE
D
PTC14 FB_AD25
— — — 74 87 B5 PTC15 DISABLE
D
PTC15 FB_AD24
— — — — 88 — VSS VSS VSS
— — — — 89 — VDD VDD VDD
— — B5 75 90 D5 PTC16 DISABLE
D
PTC16 LPUART0
_RX
FB_CS5_
b/
FB_TSIZ1/
FB_BE23_
16_
BLS15_8_
b
— — A5 76 91 C4 PTC17 DISABLE
D
PTC17 LPUART0
_TX
FB_CS4_
b/
FB_TSIZ0/
Pinout
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
220 NXP Semiconductors
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