64
MAP
BGA
64
LQFP
80
WLC
SP
88
QFN
100
LQFP
121
MAP
BGA
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EZPORT
FB_BE31_
24_BLS7_
0_b
— — — 77 92 B4 PTC18 DISABLE
D
PTC18 LPUART0
_RTS_b
FB_
TBST_b/
FB_CS2_
b/
FB_BE15_
8_BLS23_
16_b
— — — 78 — A4 PTC19 DISABLE
D
PTC19 LPUART0
_CTS_b
FB_CS3_
b/
FB_BE7_
0_BLS31_
24_b
FB_TA_b
C3 57 C5 79 93 D4 PTD0/
LLWU_
P12
DISABLE
D
PTD0/
LLWU_
P12
SPI0_
PCS0
UART2_
RTS_b
FTM3_
CH0
FB_ALE/
FB_CS1_
b/
FB_TS_b
LPUART0
_RTS_b
A4 58 B6 80 94 D3 PTD1 ADC0_
SE5b
ADC0_
SE5b
PTD1 SPI0_SCK UART2_
CTS_b
FTM3_
CH1
FB_CS0_b LPUART0
_CTS_b
C2 59 A6 81 95 C3 PTD2/
LLWU_
P13
DISABLE
D
PTD2/
LLWU_
P13
SPI0_
SOUT
UART2_
RX
FTM3_
CH2
FB_AD4 LPUART0
_RX
I2C0_SCL
B3 60 C6 82 96 B3 PTD3 DISABLE
D
PTD3 SPI0_SIN UART2_
TX
FTM3_
CH3
FB_AD3 LPUART0
_TX
I2C0_SDA
A3 61 B7 83 97 A3 PTD4/
LLWU_
P14
DISABLE
D
PTD4/
LLWU_
P14
SPI0_
PCS1
UART0_
RTS_b
FTM0_
CH4
FB_AD2 EWM_IN SPI1_
PCS0
C1 62 A7 84 98 A2 PTD5 ADC0_
SE6b
ADC0_
SE6b
PTD5 SPI0_
PCS2
UART0_
CTS_b
FTM0_
CH5
FB_AD1 EWM_
OUT_b
SPI1_SCK
— — — 85 — F7 VSS VSS VSS
— — — 86 — E7 VDD VDD VDD
B2 63 C7 87 99 B2 PTD6/
LLWU_
P15
ADC0_
SE7b
ADC0_
SE7b
PTD6/
LLWU_
P15
SPI0_
PCS3
UART0_
RX
FTM0_
CH6
FB_AD0 FTM0_
FLT0
SPI1_
SOUT
A2 64 D7 88 100 A1 PTD7 DISABLE
D
PTD7 UART0_
TX
FTM0_
CH7
FTM0_
FLT1
SPI1_SIN
— — — — — A10 PTD8 DISABLE
D
PTD8 I2C0_SCL LPUART0
_RX
FB_A16
— — — — — A9 PTD9 DISABLE
D
PTD9 I2C0_SDA LPUART0
_TX
FB_A17
— — — — — B1 PTD10 DISABLE
D
PTD10 LPUART0
_RTS_b
FB_A18
— — — — — C2 PTD11 DISABLE
D
PTD11 LPUART0
_CTS_b
FB_A19
— — — — — C1 PTD12 DISABLE
D
PTD12 FTM3_
FLT0
FB_A20
Chapter 10 Signal Multiplexing and Signal Descriptions
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 221