NXP Semiconductors K22F series - Page 30

Section number Title Page
37.3 Functional Description..................................................................................................................................................862
37.3.1 Voltage Reference Disabled, SC[VREFEN] = 0......................................................................................... 863
37.3.2 Voltage Reference Enabled, SC[VREFEN] = 1.......................................................................................... 863
37.3.3 Internal voltage regulator.............................................................................................................................864
37.4 Initialization/Application Information..........................................................................................................................865
Chapter 38
Programmable Delay Block (PDB)
38.1 Introduction...................................................................................................................................................................867
38.1.1 Features........................................................................................................................................................ 867
38.1.2 Implementation............................................................................................................................................ 868
38.1.3 Back-to-back acknowledgment connections................................................................................................869
38.1.4 DAC External Trigger Input Connections................................................................................................... 869
38.1.5 Block diagram..............................................................................................................................................869
38.1.6 Modes of operation...................................................................................................................................... 871
38.2 PDB signal descriptions................................................................................................................................................871
38.3 Memory map and register definition.............................................................................................................................871
38.3.1
Status and Control register (PDBx_SC).......................................................................................................873
38.3.2
Modulus register (PDBx_MOD)..................................................................................................................876
38.3.3
Counter register (PDBx_CNT).....................................................................................................................876
38.3.4
Interrupt Delay register (PDBx_IDLY)....................................................................................................... 877
38.3.5
Channel n Control register 1 (PDBx_CHnC1).............................................................................................877
38.3.6
Channel n Status register (PDBx_CHnS).....................................................................................................878
38.3.7
Channel n Delay 0 register (PDBx_CHnDLY0)..........................................................................................879
38.3.8
Channel n Delay 1 register (PDBx_CHnDLY1)..........................................................................................880
38.3.9
DAC Interval Trigger n Control register (PDBx_DACINTCn)...................................................................880
38.3.10
DAC Interval n register (PDBx_DACINTn)............................................................................................... 881
38.3.11
Pulse-Out n Enable register (PDBx_POEN)................................................................................................882
38.3.12
Pulse-Out n Delay register (PDBx_POnDLY).............................................................................................882
38.4 Functional description...................................................................................................................................................883
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
30 NXP Semiconductors