NXP Semiconductors K22F series - Page 34

Section number Title Page
40.3.2
Timer Load Value Register (PIT_LDVALn)...............................................................................................1033
40.3.3
Current Timer Value Register (PIT_CVALn)............................................................................................. 1033
40.3.4
Timer Control Register (PIT_TCTRLn)......................................................................................................1034
40.3.5
Timer Flag Register (PIT_TFLGn)..............................................................................................................1034
40.4 Functional description...................................................................................................................................................1035
40.4.1 General operation.........................................................................................................................................1035
40.4.2 Interrupts...................................................................................................................................................... 1037
40.4.3 Chained timers............................................................................................................................................. 1037
40.5 Initialization and application information.....................................................................................................................1037
40.6 Example configuration for chained timers....................................................................................................................1038
Chapter 41
Low-Power Timer (LPTMR)
41.1 Introduction...................................................................................................................................................................1041
41.1.1 Features........................................................................................................................................................ 1041
41.1.2 Modes of operation...................................................................................................................................... 1041
41.2 LPTMR signal descriptions.......................................................................................................................................... 1042
41.2.1 Detailed signal descriptions......................................................................................................................... 1042
41.3 Memory map and register definition.............................................................................................................................1042
41.3.1
Low Power Timer Control Status Register (LPTMRx_CSR)......................................................................1043
41.3.2
Low Power Timer Prescale Register (LPTMRx_PSR)................................................................................1044
41.3.3
Low Power Timer Compare Register (LPTMRx_CMR).............................................................................1046
41.3.4
Low Power Timer Counter Register (LPTMRx_CNR)............................................................................... 1046
41.4 Functional description...................................................................................................................................................1047
41.4.1 LPTMR power and reset..............................................................................................................................1047
41.4.2 LPTMR clocking..........................................................................................................................................1047
41.4.3 LPTMR prescaler/glitch filter......................................................................................................................1047
41.4.4 LPTMR compare..........................................................................................................................................1049
41.4.5 LPTMR counter........................................................................................................................................... 1049
41.4.6 LPTMR hardware trigger.............................................................................................................................1050
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
34 NXP Semiconductors