NXP Semiconductors K22F series - Page 33

Section number Title Page
39.4.14 Deadtime insertion....................................................................................................................................... 992
39.4.15 Output mask................................................................................................................................................. 995
39.4.16 Fault control................................................................................................................................................. 995
39.4.17 Polarity control.............................................................................................................................................999
39.4.18 Initialization................................................................................................................................................. 1000
39.4.19 Features priority........................................................................................................................................... 1000
39.4.20 Channel trigger output................................................................................................................................. 1001
39.4.21 Initialization trigger......................................................................................................................................1002
39.4.22 Capture Test mode....................................................................................................................................... 1005
39.4.23 DMA............................................................................................................................................................ 1005
39.4.24 Dual Edge Capture mode............................................................................................................................. 1006
39.4.25 Quadrature Decoder mode........................................................................................................................... 1014
39.4.26 BDM mode...................................................................................................................................................1019
39.4.27 Intermediate load..........................................................................................................................................1020
39.4.28 Global time base (GTB)...............................................................................................................................1022
39.5 Reset overview..............................................................................................................................................................1024
39.6 FTM Interrupts..............................................................................................................................................................1025
39.6.1 Timer Overflow Interrupt.............................................................................................................................1026
39.6.2 Channel (n) Interrupt....................................................................................................................................1026
39.6.3 Fault Interrupt.............................................................................................................................................. 1026
39.7 Initialization Procedure.................................................................................................................................................1026
Chapter 40
Periodic Interrupt Timer (PIT)
40.1 Introduction...................................................................................................................................................................1029
40.1.1 Block diagram..............................................................................................................................................1029
40.1.2 Features........................................................................................................................................................ 1030
40.2 Signal description..........................................................................................................................................................1030
40.3 Memory map/register description.................................................................................................................................1031
40.3.1 PIT Module Control Register (PIT_MCR).................................................................................................. 1031
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 33