NXP Semiconductors K22F series

To Next Page

To Previous Page

Section number Title Page

46.3.6

I2C Control Register 2 (I2Cx_C2)...............................................................................................................1190

46.3.7

I2C Programmable Input Glitch Filter Register (I2Cx_FLT)...................................................................... 1191

46.3.8

I2C Range Address register (I2Cx_RA)...................................................................................................... 1193

46.3.9

I2C SMBus Control and Status register (I2Cx_SMB).................................................................................1193

46.3.10

I2C Address Register 2 (I2Cx_A2)..............................................................................................................1195

46.3.11

I2C SCL Low Timeout Register High (I2Cx_SLTH)..................................................................................1195

46.3.12

I2C SCL Low Timeout Register Low (I2Cx_SLTL)...................................................................................1196

46.4 Functional description...................................................................................................................................................1196

46.4.1 I2C protocol................................................................................................................................................. 1196

46.4.2 10-bit address............................................................................................................................................... 1201

46.4.3 Address matching.........................................................................................................................................1203

46.4.4 System management bus specification........................................................................................................ 1204

46.4.5 Resets........................................................................................................................................................... 1206

46.4.6 Interrupts...................................................................................................................................................... 1206

46.4.7 Programmable input glitch filter..................................................................................................................1209

46.4.8 Address matching wake-up..........................................................................................................................1209

46.4.9 DMA support............................................................................................................................................... 1210

46.5 Initialization/application information........................................................................................................................... 1211

Chapter 47

Universal Asynchronous Receiver/Transmitter (UART)

47.1 Introduction...................................................................................................................................................................1215

47.1.1 Features........................................................................................................................................................ 1215

47.1.2 Modes of operation...................................................................................................................................... 1217

47.2 UART signal descriptions.............................................................................................................................................1218

47.2.1 Detailed signal descriptions......................................................................................................................... 1218

47.3 Memory map and registers............................................................................................................................................1219

47.3.1

UART Baud Rate Registers: High (UARTx_BDH).................................................................................... 1224

47.3.2

UART Baud Rate Registers: Low (UARTx_BDL)..................................................................................... 1225

47.3.3

UART Control Register 1 (UARTx_C1)..................................................................................................... 1226

K22F Sub-Family Reference Manual, Rev. 4, 08/2016

40 NXP Semiconductors