Section number Title Page
51.3.2 Bypass register............................................................................................................................................. 1387
51.3.3 Device identification register.......................................................................................................................1387
51.3.4 Boundary scan register.................................................................................................................................1388
51.4 Functional description...................................................................................................................................................1389
51.4.1 JTAGC reset configuration.......................................................................................................................... 1389
51.4.2 IEEE 1149.1-2001 (JTAG) Test Access Port.............................................................................................. 1389
51.4.3 TAP controller state machine.......................................................................................................................1389
51.4.4 JTAGC block instructions............................................................................................................................1391
51.4.5 Boundary scan..............................................................................................................................................1394
51.5 Initialization/Application information.......................................................................................................................... 1394
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
46 NXP Semiconductors