25.5.3.1 Example 1: Moving from FEI to PEE mode: External Crystal =
4 MHz, MCGOUTCLK frequency = 48 MHz
In this example, the MCG will move through the proper operational modes from FEI to
PEE to achieve 48 MHz MCGOUTCLK frequency from 4 MHz external crystal
reference. First, the code sequence will be described. Then there is a flowchart that
illustrates the sequence.
1. First, FEI must transition to FBE mode:
a. C2 = 0x2C
• C2[RANGE] set to 2'b01 because the frequency of 4 MHz is within the high
frequency range.
• C2[HGO] set to 1 to configure the crystal oscillator for high gain operation.
• C2[EREFS] set to 1, because a crystal is being used.
b. C1 = 0x90
• C1[CLKS] set to 2'b10 to select external reference clock as system clock
source
• C1[FRDIV] set to 3'b010, or divide-by-128 because 4 MHz / 128 = 31.25
kHz which is in the 31.25 kHz to 39.0625 kHz range required by the FLL
• C1[IREFS] cleared to 0, selecting the external reference clock and enabling
the external oscillator.
c. Loop until S[OSCINIT0] is 1, indicating the crystal selected by C2[EREFS0] has
been initialized.
d. Loop until S[IREFST] is 0, indicating the external reference is the current source
for the reference clock.
e. Loop until S[CLKST] is 2'b10, indicating that the external reference clock is
selected to feed MCGOUTCLK.
2. Then configure C5[PRDIV0] to generate correct PLL reference frequency.
a. C5 = 0x01
• C5[PRDIV] set to 5'b00001, or divide-by-2 resulting in a pll reference
frequency of 4MHz/2 = 2 MHz.
3. Then, FBE must transition either directly to PBE mode or first through BLPE mode
and then to PBE mode:
Chapter 25 Multipurpose Clock Generator (MCG)
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 569
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