FB_CSCRn field descriptions
Field Description
31–26
SWS
Secondary Wait States
Used only when the SWSEN bit is 1b. Specifies the number of wait states inserted before an internal
transfer acknowledge is generated for a burst transfer (except for the first termination, which is controlled
by WS).
25–24
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
23
SWSEN
Secondary Wait State Enable
0 Disabled. A number of wait states (specified by WS) are inserted before an internal transfer
acknowledge is generated for all transfers.
1 Enabled. A number of wait states (specified by SWS) are inserted before an internal transfer
acknowledge is generated for burst transfer secondary terminations.
22
EXTS
Extended Transfer Start/Extended Address Latch Enable
Controls how long FB_TS /FB_ALE is asserted.
0 Disabled. FB_TS /FB_ALE asserts for one bus clock cycle.
1
Enabled. FB_TS /FB_ALE remains asserted until the first positive clock edge after FB_CSn asserts.
21–20
ASET
Address Setup
Controls when the chip-select is asserted with respect to assertion of a valid address and attributes.
00 Assert FB_CSn on the first rising clock edge after the address is asserted (default for all but
FB_CS0 ).
01 Assert FB_CSn on the second rising clock edge after the address is asserted.
10 Assert FB_CSn on the third rising clock edge after the address is asserted.
11 Assert FB_CSn on the fourth rising clock edge after the address is asserted (default for FB_CS0 ).
19–18
RDAH
Read Address Hold or Deselect
Controls the address and attribute hold time after the termination during a read cycle that hits in the
associated chip-select's address space.
NOTE:
• The hold time applies only at the end of a transfer. Therefore, during a burst transfer or a
transfer to a port size smaller than the transfer size, the hold time is only added after the
last bus cycle.
• The number of cycles the address and attributes are held after FB_CSn deassertion
depends on the value of the AA bit.
00 When AA is 1b, 1 cycle. When AA is 0b, 0 cycles.
01 When AA is 1b, 2 cycles. When AA is 0b, 1 cycle.
10 When AA is 1b, 3 cycles. When AA is 0b, 2 cycles.
11 When AA is 1b, 4 cycles. When AA is 0b, 3 cycles.
17–16
WRAH
Write Address Hold or Deselect
Controls the address, data, and attribute hold time after the termination of a write cycle that hits in the
associated chip-select's address space.
NOTE:
The hold time applies only at the end of a transfer. Therefore, during a burst transfer or a transfer
to a port size smaller than the transfer size, the hold time is only added after the last bus cycle.
00 1 cycle (default for all but FB_CS0 )
01 2 cycles
Table continues on the next page...
Memory Map/Register Definition
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
700 NXP Semiconductors
To Next Page
Loading...
