FB_CSCRn field descriptions (continued)
Field Description
10 3 cycles
11 4 cycles (default for FB_CS0 )
15–10
WS
Wait States
Specifies the number of wait states inserted after FlexBus asserts the associated chip-select and before
an internal transfer acknowledge is generated (WS = 00h inserts 0 wait states, ..., WS = 3Fh inserts 63
wait states).
9
BLS
Byte-Lane Shift
Specifies if data on FB_AD appears left-aligned or right-aligned during the data phase of a FlexBus
access.
0 Not shifted. Data is left-aligned on FB_AD.
1 Shifted. Data is right-aligned on FB_AD.
8
AA
Auto-Acknowledge Enable
Asserts the internal transfer acknowledge for accesses specified by the chip-select address.
NOTE:
If AA is 1b for a corresponding FB_CSn and the external system asserts an external FB_TA
before the wait-state countdown asserts the internal FB_TA, the cycle is terminated. Burst cycles
increment the address bus between each internal termination.
NOTE:
This field must be 1b if CSPMCR disables FB_TA.
0 Disabled. No internal transfer acknowledge is asserted and the cycle is terminated externally.
1 Enabled. Internal transfer acknowledge is asserted as specified by WS.
7–6
PS
Port Size
Specifies the data port width of the associated chip-select, and determines where data is driven during
write cycles and where data is sampled during read cycles.
00 32-bit port size. Valid data is sampled and driven on FB_D[31:0].
01 8-bit port size. Valid data is sampled and driven on FB_D[31:24] when BLS is 0b, or FB_D[7:0] when
BLS is 1b.
1X 16-bit port size. Valid data is sampled and driven on FB_D[31:16] when BLS is 0b, or FB_D[15:0]
when BLS is 1b.
5
BEM
Byte-Enable Mode
Specifies whether the corresponding FB_BE is asserted for read accesses. Certain memories have byte
enables that must be asserted during reads and writes. Write 1b to the BEM bit in the relevant CSCR to
provide the appropriate mode of byte enable support for these SRAMs.
0 FB_BE is asserted for data write only.
1
FB_BE is asserted for data read and write accesses.
4
BSTR
Burst-Read Enable
Specifies whether burst reads are enabled for memory associated with each chip select.
0 Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst reads.
For example, a 32-bit read from an 8-bit port is broken into four 8-bit reads.
1 Enabled. Enables data burst reads larger than the specified port size, including 32-bit reads from 8-
and 16-bit ports, 16-bit reads from 8-bit ports, and line reads from 8-, 16-, and 32-bit ports.
Table continues on the next page...
Chapter 31 External Bus Interface (FlexBus)
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 701
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