31.4.12.1 Enabling and inhibiting burst
The CSCRn registers enable bursting for reads, writes, or both.
Memory spaces can be declared burst-inhibited for reads and writes by writing 0b to the
appropriate CSCRn[BSTR] and CSCRn[BSTW] fields.
31.4.12.2 Transfer size and port size translation
With bursting disabled, any transfer larger than the port size breaks into multiple
individual transfers (e.g. <Addr><Data><Addr+1><Data><Addr+2><Data>). With
bursting enabled, any transfer larger than the port size results in a burst cycle of multiple
beats (e.g. <Addr><Data><Data><Data>). The following table shows the result of such
transfer translations.
Port size PS[1:0]
Transfer size FB_TSIZ[1:0]
Burst-inhibited: Number of transfers
Burst enabled: Number of beats
01b (8 bit) 10b (16 bits) 2
00b (32 bits) 4
11b (16 bytes) 16
1Xb (16 bit) 00b (32 bits) 2
11b (16 bytes) 8
00b (32 bit) 11b (line) 4
The FlexBus can support X-1-1-1 burst cycles to maximize system performance, where X
is the primary number of wait states (max 63). Delaying termination of the cycle can add
wait states. If internal termination is used, different wait state counters can be used for the
first access and the following beats.
31.4.12.3
32-bit-Read burst from 8-Bit port 2-1-1-1 (no wait states)
The following figure shows a 32-bit read to an 8-bit external chip programmed for burst
enable. The transfer results in a 4-beat burst and the data is driven on FB_AD[31:24].
The transfer size is driven at 32-bit (00b) throughout the bus cycle.
Note
• In non-multiplexed address/data mode: the address on
FB_A increments only during internally-terminated burst
Chapter 31 External Bus Interface (FlexBus)
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 729
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