account for this, or a wait state must be added. The first address
is driven throughout the entire burst for externally-terminated
cycles.
In multiplexed address/data mode, the address is driven on
FB_AD only during the first cycle for internally- and
externally-terminated cycles.
Address
Address
Data Data Data Data
Add+1 Add+2
Add+3
FB_CLK
FB_TBST
TSIZ=00
AA=1
AA=1
AA=0
FB_RW
FB_TS
FB_ALE
FB_OEn
FB_BE/BWEn
FB_TA
FB_TSIZ[1:0]
AA=0
FB_CSn
32-bit Read Burst from 8-bit port 3-1-1-1, with Address Setup and Hold
BEM=1
BEM=0
S0 AS S2 S2 S2S1 S2 AH S3
Address Setup
S0
Address Hold
If AA=1, the address increments
If AA=0, the address stays the same
AA=1
AA=0
S0 AS S2 S2 S2S1 S2 AH S3 S0
AA=1
AA=0
Read32bBurst3111ASAH.svg
TIP
Figure 31-27. 32-bit-read burst from 8-bit port 3-1-1-1 (address setup and hold)
31.4.12.10
32-bit-write burst to 8-bit port 3-1-1-1 (address setup and
hold)
The following figure shows a write cycle with one clock of address setup and address
hold.
Functional description
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
736 NXP Semiconductors