To allow sequential conversions of the ADC to be triggered by internal peripherals, the
ADC can have more than one status and control register: one for each conversion. The
SC1B–SC1n registers indicate potentially multiple SC1 registers for use only in hardware
trigger mode. See the chip configuration information about the number of SC1n registers
specific to this device. The SC1n registers have identical fields, and are used in a "ping-
pong" approach to control ADC operation.
At any one point in time, only one of the SC1n registers is actively controlling ADC
conversions. Updating SC1A while SC1n is actively controlling a conversion is allowed,
and vice-versa for any of the SC1n registers specific to this MCU.
Writing SC1A while SC1A is actively controlling a conversion aborts the current
conversion. In Software Trigger mode, when SC2[ADTRG]=0, writes to SC1A
subsequently initiate a new conversion, if SC1[ADCH] contains a value other than all 1s
(module disabled).
Writing any of the SC1n registers while that specific SC1n register is actively controlling
a conversion aborts the current conversion. None of the SC1B-SC1n registers are used for
software trigger operation and therefore writes to the SC1B–SC1n registers do not initiate
a new conversion.
Address:
Base address + 0h offset + (4d × i), where i=0d to 1d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
COCO
AIEN DIFF ADCH
W
Reset
0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1
Chapter 34 Analog-to-Digital Converter (ADC)
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 769
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