Accesses to the flash memory ranges outside the amount of Flash on the device causes
the bus cycle to be terminated with an error followed by the appropriate response in the
requesting bus master. Read collision events in which flash memory is accessed while a
flash memory resource is being manipulated by a flash command also generates a bus
error response.
3.5.1.4 Flash Security
How flash security is implemented on this device is described in Chip Security.
3.5.1.5 Flash Program Restrictions
The flash memory on this device should not be programmed or erased while operating in
High Speed Run or VLPR power modes.
3.5.1.6 Flash Modes
The flash memory operates in NVM normal and NVM special modes. The flash memory
enters NVM special mode when the EzPort is enabled (EZP_CS asserted during reset).
Otherwise, flash memory operates in NVM normal mode.
3.5.1.7
Erase All Flash Contents
The flash of the MCU is protected from erasing all of the flash contents by the
FTFA_FSEC[MEEN] bits. If the bits are set to 'b10 mass erase is disabled. An Erase All
Flash Blocks operation can be launched by software through a series of peripheral bus
writes to flash registers. In addition the entire flash memory may be erased external to the
flash memory from the SWJ-DP debug port by setting DAP_CONTROL[0].
DAP_STATUS[0] is set to indicate the mass erase command has been accepted.
DAP_STATUS[0] is cleared when the mass erase completes.
The EzPort can also initiate an erase of flash contents by issuing a bulk erase (BE)
command. See the EzPort chapter for more details.
3.5.1.8
FTF_FOPT Register
The flash memory's FTF_FOPT register allows the user to customize the operation of the
MCU at boot time. See FOPT boot options for details of its definition.
Memories and memory interfaces
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
86 NXP Semiconductors
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