NXP Semiconductors K22F series - Page 908

FTMx_CnSC field descriptions
Field Description
31–8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
7
CHF
Channel Flag
Set by hardware when an event occurs on the channel. CHF is cleared by reading the CSC register while
CHnF is set and then writing a 0 to the CHF bit. Writing a 1 to CHF has no effect.
If another event occurs between the read and write operations, the write operation has no effect; therefore,
CHF remains set indicating an event has occurred. In this case a CHF interrupt request is not lost due to
the clearing sequence for a previous CHF.
0 No channel event has occurred.
1 A channel event has occurred.
6
CHIE
Channel Interrupt Enable
Enables channel interrupts.
0 Disable channel interrupts. Use software polling.
1 Enable channel interrupts.
5
MSB
Channel Mode Select
Used for further selections in the channel logic. Its functionality is dependent on the channel mode. See
Table 39-2 .
This field is write protected. It can be written only when MODE[WPDIS] = 1.
4
MSA
Channel Mode Select
Used for further selections in the channel logic. Its functionality is dependent on the channel mode. See
Table 39-2 .
This field is write protected. It can be written only when MODE[WPDIS] = 1.
3
ELSB
Edge or Level Select
The functionality of ELSB and ELSA depends on the channel mode. See Table 39-2 .
This field is write protected. It can be written only when MODE[WPDIS] = 1.
2
ELSA
Edge or Level Select
The functionality of ELSB and ELSA depends on the channel mode. See Table 39-2 .
This field is write protected. It can be written only when MODE[WPDIS] = 1.
1
ICRST
FTM counter reset by the selected input capture event.
FTM counter reset is driven by the selected event of the channel (n) in the Input Capture mode.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 FTM counter is not reset when the selected channel (n) input event is detected.
1 FTM counter is reset when the selected channel (n) input event is detected.
0
DMA
DMA Enable
Enables DMA transfers for the channel.
0 Disable DMA transfers.
1 Enable DMA transfers.
Memory map and register definition
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
908 NXP Semiconductors