FTM counter
0 0 0
1 1 11 1
2 2 22 23 3 33 34 4 4
FTM counting is up-down
TOF bit
set TOF bit set TOF bit
period of FTM counter clock
period of counting = 2 x (MOD - CNTIN) x period of FTM counter clock
= 2 x MOD x period of FTM counter clock
CNTIN = 0x0000
MOD = 0x0004
Figure 39-7. Example of up-down counting when CNTIN = 0x0000
Note
When CNTIN is different from zero in the up-down counting, a
valid CPWM signal is generated:
• if CnV > CNTIN, or
• if CnV = 0 or if CnV[15] = 1. In this case, 0% CPWM is
generated.
39.4.3.3
Free running counter
If (FTMEN = 0) and (MOD = 0x0000 or MOD = 0xFFFF), the FTM counter is a free
running counter. In this case, the FTM counter runs free from 0x0000 through 0xFFFF
and the TOF bit is set when the FTM counter changes from 0xFFFF to 0x0000. See the
following figure.
FTM counter
0x00040x0004
0xFFFE
0xFFFF
0x0003
0x0000
0x0001
0x0002 0x0003 0x0005 0x0006
TOF bit
... ... ...
FTMEN = 0
set TOF bit
MOD = 0x0000
Figure 39-8. Example when the FTM counter is free running
The FTM counter is also a free running counter when:
Functional description
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
952 NXP Semiconductors
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