channel (n) input
synchronizer
1
is filter
enabled?
edge
detector
was falling
edge selected?
was rising
edge selected?
rising edge
falling edge
0
1
1
0
0 0
CnV
FTM counter
DQ
CLK
DQ
CLK
system clock
channel (n) interrupt
CHnIE
CHnF
Filter*
0
* Filtering function is only available in the inputs of channel 0, 1, 2, and 3
Figure 39-11. Input Capture mode
If the channel input does not have a filter enabled, then the input signal is always delayed
3 rising edges of the system clock, that is, two rising edges to the synchronizer plus one
more rising edge to the edge detector. In other words, the CHnF bit is set on the third
rising edge of the system clock after a valid edge occurs on the channel input.
39.4.4.1
Filter for Input Capture mode
The filter function is only available on channels 0, 1, 2, and 3.
First, the input signal is synchronized by the system clock. Following synchronization,
the input signal enters the filter block. See the following figure.
system clock
filter counter
Logic to define
the filter output
filter output
divided by 4
channel (n) input after
the synchronizer
Logic to control
the filter counter
CHnFVAL[3:0]
C
S
Q
CLK
Figure 39-12. Channel input filter
When there is a state change in the input signal, the counter is reset and starts counting
up. As long as the new state is stable on the input, the counter continues to increment.
When the counter is equal to CHnFVAL[3:0], the state change of the input signal is
validated. It is then transmitted as a pulse edge to the edge detector.
Chapter 39 FlexTimer Module (FTM)
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
NXP Semiconductors 955
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