If the opposite edge appears on the input signal before it can be validated, the counter is
reset. At the next input transition, the counter starts counting again. Any pulse that is
shorter than the minimum value selected by CHnFVAL[3:0] (× 4 system clocks) is
regarded as a glitch and is not passed on to the edge detector. A timing diagram of the
input filter is shown in the following figure.
The filter function is disabled when CHnFVAL[3:0] bits are zero. In this case, the input
signal is delayed 3 rising edges of the system clock. If (CHnFVAL[3:0] ≠ 0000), then the
input signal is delayed by the minimum pulse width (CHnFVAL[3:0] × 4 system clocks)
plus a further 4 rising edges of the system clock: two rising edges to the synchronizer,
one rising edge to the filter output, plus one more to the edge detector. In other words,
CHnF is set (4 + 4 × CHnFVAL[3:0]) system clock periods after a valid edge occurs on
the channel input.
The clock for the counter in the channel input filter is the system clock divided by 4.
CHnFVAL[3:0] = 0100
(binary value)
channel (n) input
after the synchronizer
counte r
filter output *
system clock divided by 4
Time
* Note: Filter output is delayed one system clock of filter counter logic output.
Figure 39-13. Channel input filter example
The figure below shows an example of input capture with filter enabled and the delay
added by each part of the input capture logic. Note that the input signal is delayed only by
the synchronizer and edge dector logic if the filter is disabled.
Functional description
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
956 NXP Semiconductors
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