39.4.10.1 CNTIN register update
The following table describes when CNTIN register is updated:
Table 39-5. CNTIN register update
When Then CNTIN register is updated
CLKS[1:0] = 0:0 When CNTIN register is written, independent of FTMEN bit.
• FTMEN = 0, or
• CNTINC = 0
At the next system clock after CNTIN was written.
• FTMEN = 1,
• SYNCMODE = 1, and
• CNTINC = 1
By the CNTIN register synchronization.
39.4.10.2 MOD register update
The following table describes when MOD register is updated:
Table 39-6. MOD register update
When Then MOD register is updated
CLKS[1:0] = 0:0 When MOD register is written, independent of FTMEN bit.
• CLKS[1:0] ≠0:0, and
• FTMEN = 0
According to the CPWMS bit, that is:
• If the selected mode is not CPWM then MOD register is updated after MOD
register was written and the FTM counter changes from MOD to CNTIN. If
the FTM counter is at free-running counter mode then this update occurs
when the FTM counter changes from 0xFFFF to 0x0000.
• If the selected mode is CPWM then MOD register is updated after MOD
register was written and the FTM counter changes from MOD to (MOD –
0x0001).
• CLKS[1:0] ≠0:0, and
• FTMEN = 1
By the MOD register synchronization.
39.4.10.3 CnV register update
The following table describes when CnV register is updated:
Table 39-7. CnV register update
When Then CnV register is updated
CLKS[1:0] = 0:0 When CnV register is written, independent of FTMEN bit.
• CLKS[1:0] ≠0:0, and
• FTMEN = 0
According to the selected mode, that is:
Table continues on the next page...
Functional description
K22F Sub-Family Reference Manual, Rev. 4, 08/2016
972 NXP Semiconductors
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